adamsogood
Member level 1
Hi, Guys,
I just finished an HDLC(High-level data link control)-based protocol payload deframer on Xilinx FPGAs. My design is targeted on PCI-express bus. Does anyone suggest me how to make a test bench and verify my design? thank you.
I just finished an HDLC(High-level data link control)-based protocol payload deframer on Xilinx FPGAs. My design is targeted on PCI-express bus. Does anyone suggest me how to make a test bench and verify my design? thank you.