UltraGreen
Junior Member level 3
How to introduce small delay in clock path ?
Hello all,
How can I add a small fixed ( known ) delay in clock path manually in fpga ?
suppose I have a setup violation and there is no hold violation , then can I add some delay in the clock path between the register to give some extra margin for fixing set up violation. I know this is not the best way to solve set up violation , but out of curiosity I want to know, how can I add fix delay in fpga in clock path without making change in rtl.
FPGA = virterx ultrascale
IDE = vivado 2015
Thanks
Hello all,
How can I add a small fixed ( known ) delay in clock path manually in fpga ?
suppose I have a setup violation and there is no hold violation , then can I add some delay in the clock path between the register to give some extra margin for fixing set up violation. I know this is not the best way to solve set up violation , but out of curiosity I want to know, how can I add fix delay in fpga in clock path without making change in rtl.
FPGA = virterx ultrascale
IDE = vivado 2015
Thanks