[SOLVED] How to do sampling in VHDL (ADC)?

[mrflibble]

Those analog weight are constants yes? If so then you know them in advance, and you can convert those analog values to a NUMBER that is represented in digital form. This digital form, you know, a number, is then stuffed in your fpga. Either at runtime or as constants in your VHDL code.

.. My senior told me that we have to use ADC separately and than we will be getting 16 bits, now this digital data will be expressed in INphase and Q-phase. ...

And if that still is unclear, by now I suggest you talk with this senior on the project, and try to clear up these analog related doubts. This seems to be DSP 101, so hopefully a 60 minutes talk with the guy that knows more about the project should be more meaningful than back and forth "but it is analog" posts.

 

[Nirdeshika]

I will be designing a real system. but first i have to write software for 2 beams then for 8 beams.

You are saying that if i feed these weights directly to fpga memory, it will automatically represent these values by their digital values?

 

[mrflibble]

I am saying that if you intelligently convert those analog weight to a digital representation, then yes, it will automatically represent these values by their digital values. In related news: throwing milk, cream and sugar in the fridge will automatically represent ice cream! Yum!

 

[Nirdeshika]

yes they are constant and i have these weights in matrix form.

 

[mrflibble]

Well, problem solved then!

 

[Nirdeshika]

yeah i got it. Thanx :razz:

 

[barry]

@barry: but they are analog!

They are NOT analog; they are NUMBERS.

 

[Zerox100]

FPGA story just starts after sampling. It means you supposed to have a digital data stream that has been already sampled (e.g. by ADC). In FPGA you are about processing parts (Filtering, Mixing, ...).

 

[Nirdeshika]

They are NOT analog; they are NUMBERS.

now i'm taking just the digital representation of weights....

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FPGA story just starts after sampling. It means you supposed to have a digital data stream that has been already sampled (e.g. by ADC). In FPGA you are about processing parts (Filtering, Mixing, ...).

I'm not using ADC here, But i want an output which is quantized waveform.

 

[TrickyDicky]

But the FPGA input HAS to be digital, and the output HAS to to be digital. You cannot sample an analogue signal in an FPGA. You need an ADC for that.

 

[Zerox100]

Do you have "load cell"? (Digital or Analog?)

 

[Nirdeshika]

But the FPGA input HAS to be digital, and the output HAS to to be digital. You cannot sample an analogue signal in an FPGA. You need an ADC for that.

does it mean that i cannot use just the digital representation of weight?

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Do you have "load cell"? (Digital or Analog?)

load cells?

 

[Zerox100]

LoadCell is for measuring weight!!!

 

[mrflibble]

He doesn't have load cells. Consider the "weight" as a "factor for multiplication".

 

[Zerox100]

And what about source of "P"? What is it?

 

[vlsi_maniac]

Can anyone comment on the attached PDF from Lattice Semi.
They have implemented an ADC inside FPGA.
How do we write a Verilog Code for such stuff ?

 

[FvM]

Basic sigma-delta ADCs like that shown in Lattice paper can be often found in simple FPGA evaluation boards. You should also find code examples for it.

For a systematical design, you can refer to SD literature. A specific point of the shown circuit is that a LVDS receiver is used as analog comparator, although it's not specified for this operation. For this reason it's impossible to predict the analog performance.

In the context of this thread about analog signal processing for beamforming, a SD-ADC with maximum 50 kHz bandwidth is simply off-topic.