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[SOLVED] How to do sampling in VHDL (ADC)?

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Nirdeshika

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I have a project on Digital Beam Forming. I get 32 Beams from antenna array and i give this as input to DBF and it gives 8 beams as output. Now These beams from antenna array have amplitude and phase. This is an exponentiaL signal. Ex: one beam id A*e^(jΦ) where A=amplitude in dB, Φ=phase. Now i have to convert it into digital form. For that i need ADC. Finally i would be doing this on a FPGA card. I saw on some forum that we can not implement ADC on FPGA card. So First i need to sample the signal, and then quantize and encode, I dont know how to start sampling with VHDL code? :oops:
 

You can't sample with VHDL code; but you can read the output of an ADC with VHDL code. Yes, you CAN sample with an FPGA card if it has an on-board ADC!!!
 

So you mean that i would not need to sample, quantize and encode the beam, i can have onborad ADC on FPGA card? Beam is an exponential signal.
 

There are fpga boards with ADCs on it. You will still be sampling etc. With those sort of boards you will have to write some vhdl code to control the ADC chip and to handle the data, etc.
 

See, I have to store output from an ADC to RAM on FPGA along with weights(which are exponential values) Than i have to perform FFT on them. These weight have to be stored in RAM. But they are analog form.
 

Everything made sense until "But they are analog form."

You sample your wavevorm, you get the data into the fpga, you perform FFT on that data. Okay, sounds good to me. So where's the problem?
 

To understand the feasibility of direct RF digitizing (with suitable ADCs) it would be interesting to know the intended frequency and dynamic range.
 

The beam may be an "exponential signal", but that's just the mathematical interpretation of the signal. The signal is a voltage (presumably) that gets converted by the ADC; the ADC doesn't care WHAT the voltage represents.
 
okk, i got it. Now i'm more clear about it. @mrfibble: My senior told me that we have to use ADC separately and than we will be getting 16 bits, now this digital data will be expressed in INphase and Q-phase. These in phase and Q-phase data will be multiplied by some weight that is stored in RAM on FPGA. and finally FFt will be performed. Now these weight are in exponential form which i was talking about.
now the only doubt i have is how can we store an analog value(weights) on FPGA card.
 

How about converting the analog values for your weights to discrete values? Then stuff that in your fpga.

There's nothing magic about it being in exponential form, those are just values like any other representation. Possibly they are a (amplitude, phase) pair if those exponential thingies are complex, but still the same applies: convert to discrete values and stuff in fpga.
 
Dont' we have any provision to store analog values on FPGA?

And if we convert them into discrete values, should we follow sampling and quantization techniques?
 

No analog storage, and yes you should quantize those values if you intend to have the fpga do any computations with them.
 

yeah that was my question that how can i do sampling in VHDL..
 

The ADC does the actual sampling. YOu need to write VHDL to access that data stream. The VHDL you write will depend on how the ADC on your board works. (ie. read the datasheet for the ADC)
 

I have to store these weights in RAM directly, so is it like that; first i will be using ADC and than storing these values in RAM?
 

Brother,

I think this XAPP may help you understand interfacing ADC with Xilinx FPGA.

You can follow this link

Well this is one example you may find others on internet.

Bests,
Shan
 

You don't need to "sample" your weights-they are just numbers, you just stuff them into ROM in your FPGA (or declare them as constants or something like that-depends on how many you have).
 

but they are analog!
It's the nature of digital signal processing to represent analog signals and parameters (e.g. the said weights) by digital quantities respectively numbers.

Are you designing a real system or just writing software for a hypothetical beam former?
 

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