How to design a high frequency PLL?

[Ritika]

I have designed a PLL works at a speed of GHz. For intial simulation i have taken simple divided by 2 counter. Now i am looking for perfect divider architecture for high frequency.

VCO output frequency is around 2GHz.

Previously i have worked on low frequency PLL and for that i used dual modulus based programmable counter.

Any of you please suggest me for hisgh frequency
1. what type of architecture
2. DFF architecture ------ as high frequeny series cmos based normal nand gate is not prefferd.
3. tips that can help me in design.

Thanks

 

[webdog]

GHz PLL

You need to tell us more...
What reference frequency? Switch speed ?
Range, or is it single frequency?

Simplest way is using ready made PLL IC which operates at above 4 GHz. You can get prescalers with dual modulus counting and then use simple CMOS logic.

 

[sekharareddy]

Re: GHz PLL

Hello Ritika,

If you are ready to go with PLL IC solution, You can proceed by using ADF4106 from analog devices.It suits better for your operating frequency.

Sekhar

 

[jecyhale]

Re: GHz PLL

Hi, speed divider is usually named pre-scaler.

It doesn't work with full swing, but works with very low swing.

So all the Digtal cell can't be used here.

 

[kspalla]

Re: GHz PLL

Hi,
Basically you need to know the specification like PLL step size, phase noise etc. You can have factional synthesizers too.

 

[trayant]

GHz PLL

probably u can try to use a latch-based divided-by-2 circuit. this is a analog design and a power hungry device. therefore, u should need to have your power budget.

this design will give u full swing.