biju4u90
Full Member level 3
How does multicycle path arise at CDC when we use asynchronous fifo?
When we cross from a faster clock domain to slower domain, we use an asynchronous FIFO to avoid data loss due to slower sampling rate at the receiving clock domain. But in the following post in this forum, it was discussed about setting multicycle path and false path in CDC.
https://www.edaboard.com/threads/134188/
When there is an asychronous FIFO, how does there come a multicycle path or false path? I ask this because, when we write data into the asynchronous FIFO, the data input to the FIFO and FIFO write are in same clock. So no clock domain crossing occurs at this point. When we read data from the FIFO, the read clock and the data fed circuit will be in same clock domain. Again, no clock domain crossing!! Please correct me if I am wrong!!
When we cross from a faster clock domain to slower domain, we use an asynchronous FIFO to avoid data loss due to slower sampling rate at the receiving clock domain. But in the following post in this forum, it was discussed about setting multicycle path and false path in CDC.
https://www.edaboard.com/threads/134188/
When there is an asychronous FIFO, how does there come a multicycle path or false path? I ask this because, when we write data into the asynchronous FIFO, the data input to the FIFO and FIFO write are in same clock. So no clock domain crossing occurs at this point. When we read data from the FIFO, the read clock and the data fed circuit will be in same clock domain. Again, no clock domain crossing!! Please correct me if I am wrong!!
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