How can i simulate this vhdl code?

[jacksparrow93]

So i wrote this code (code is working on nexys 3) and when i'm trying to simulate it (created VHDL test brench, clicked on simulate behavioral model) it just gives me errors(syntax, illegal identifier, possible infinite loop)... How can i simulate it?


Code is:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity glavni is
port(
	start_stop, reset, cp: in STD_LOGIC;
	led: out STD_LOGIC_VECTOR (6 downto 0);
	anode: buffer STD_LOGIC_VECTOR(3 downto 0)
);
end glavni;

architecture Behavioral of glavni is
signal temp: std_logic_vector (7 downto 0);
signal cp_o,cp_o1: std_logic;
signal x: std_logic_vector(1 downto 0);
signal prikaz:std_logic_vector(3 downto 0);
begin
S1: entity work.FreqDivGen generic map (100000000) port map (cp, cp_o);
S2: entity work.FreqDivGen generic map (500000) port map (cp, cp_o1);

process(cp_o, reset, start_stop)
begin
	if(reset = '1') then
		temp <= "00111011";--3B
	elsif(rising_edge(cp_o)) then
			if(temp = "00000000") then
				temp <= "00111011"; --3B	
			elsif(start_stop = '1') then
				temp <= temp - 1;
				else
					temp <= temp;
			end if;
	end if;	
end process;	

process(cp_o1) --brojac brzine 200HZ-a
begin
	if(cp_o1'event and cp_o1='1') then
		x<=x+1;

	end if;
end process;

process(x) -- Vremenski multiplekser, reagira na brojac koji je 200HZ i pali/gasi anode, prikaz znaka ovisi o trenutnom stanju FSM-a
begin
	case x is
		when "00" => anode<="1110";
		when "01" => anode<="1101";
		when  others => anode<="1111";
	end case;
end process;	



process(anode)
begin
case anode is
		when "1110" => prikaz<=temp(3 downto 0);
		when others => prikaz<=temp(7 downto 4);
			
end case;
end process;

with prikaz select
			led<= "0000001" when "0000", --0 (abcdefg)
					"1111001" when "0001", --1
					"0010010" when "0010", --2
					"0000110" when "0011", --3
					"1001100" when "0100", --4
					"0100100" when "0101", --5
					"0100000" when "0110", --6
					"0001111" when "0111", --7
					"0000000" when "1000", --8
					"0000100" when "1001", --9
					"0001000" when "1010", --a
					"1100000" when "1011", --b
					"0110001" when "1100", --c
					"1000010" when "1101", --d
					"0110000" when "1110", --e
					"0111000" when others; --f
end Behavioral;

--------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--------------------------------

entity FreqDivGen is
generic(nfCLK: natural := 100);
port(
	clk: in STD_LOGIC := '0';
	clk_o: buffer STD_LOGIC := '0'
);
end FreqDivGen;

architecture Behavioral of FreqDivGen is
begin

process(clk)
variable temp: integer range 0 to nfCLK/2 := 0;
begin
		if (clk'event and clk='1') then
			temp:=temp+1;
			if (temp>=nfCLK/2) then
				clk_o<=not clk_o;
				temp:=0;
			end if;
		end if;
		
end process;
end Behavioral;

 

[K-J]

Start by fixing all of the syntax errors, illegal identifiers, and possible infinite loops that the tool has identified for you.

Kevin

 

[FvM]

The posted code has no syntax errors, is compatible even with VHDL 1987 and has no loops at all.

Either the syntax errors are in your test bench or you compiled a different code.

 

[jacksparrow93]

Hey, i know my code has no sytax error because it's working fine on nexys 3.
I've talked to professor, he told me if i have signal i need to set value and i need to be careful for time of simulation because i have frequency divider.

here is the errors on that test branch file.

--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:   00:02:19 01/30/2017
-- Design Name:   
-- Module Name:   D:/dss/ef.vhd
-- Project Name:  dss
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: glavni
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
 
ENTITY ef IS
END ef;
 
ARCHITECTURE behavior OF ef IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT glavni
    PORT(
         start_stop : IN  std_logic;
         reset : IN  std_logic;
         cp : IN  std_logic;
         led : OUT  std_logic_vector(6 downto 0);
         anode : OUT  std_logic_vector(3 downto 0)
        );
    END COMPONENT;
    

   --Inputs
   signal start_stop : std_logic := '0';
   signal reset : std_logic := '0';
   signal cp : std_logic := '0';

 	--Outputs
   signal led : std_logic_vector(6 downto 0);
   signal anode : std_logic_vector(3 downto 0);
   -- No clocks detected in port list. Replace <clock> below with 
   -- appropriate port name 
 
   constant <clock>_period : time := 10 ns;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: glavni PORT MAP (
          start_stop => start_stop,
          reset => reset,
          cp => cp,
          led => led,
          anode => anode
        );

   -- Clock process definitions
   <clock>_process :process
   begin
		<clock> <= '0';
		wait for <clock>_period/2;
		<clock> <= '1';
		wait for <clock>_period/2;
   end process;
 

   -- Stimulus process
   stim_proc: process
   begin		
      -- hold reset state for 100 ns.
      wait for 100 ns;	

      wait for <clock>_period*10;

      -- insert stimulus here 

      wait;
   end process;

END;

Started : "Simulate Behavioral Model".

Determining files marked for global include in the design...
Running fuse...
Command Line: fuse -intstyle ise -incremental -lib secureip -o D:/dss/ef_isim_beh.exe -prj D:/dss/ef_beh.prj work.ef {}
Running: C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64\unwrapped\fuse.exe -intstyle ise -incremental -lib secureip -o D:/dss/ef_isim_beh.exe -prj D:/dss/ef_beh.prj work.ef 
ISim P.20131013 (signature 0x7708f090)
Number of CPUs detected in this system: 4
Turning on mult-threading, number of parallel sub-compilation jobs: 8 
Determining compilation order of HDL files
ERROR:HDLCompiler:488 - "D:/dss/ef.vhd" Line 64: Illegal identifier : _period
ERROR:HDLCompiler:488 - "D:/dss/ef.vhd" Line 78: Illegal identifier : _process
ERROR:HDLCompiler:488 - "D:/dss/ef.vhd" Line 81: Illegal identifier : _period
ERROR:HDLCompiler:488 - "D:/dss/ef.vhd" Line 83: Illegal identifier : _period
ERROR:HDLCompiler:488 - "D:/dss/ef.vhd" Line 93: Illegal identifier : _period
Parsing VHDL file "D:/dss/FreqDivGen.vhd" into library work
Parsing VHDL file "D:/dss/glavni.vhd" into library work
Parsing VHDL file "D:/dss/ef.vhd" into library work
ERROR:HDLCompiler:806 - "D:/dss/ef.vhd" Line 64: Syntax error near "<".
ERROR:HDLCompiler:488 - "D:/dss/ef.vhd" Line 64: Illegal identifier : _period
ERROR:HDLCompiler:806 - "D:/dss/ef.vhd" Line 78: Syntax error near "<".
ERROR:HDLCompiler:488 - "D:/dss/ef.vhd" Line 78: Illegal identifier : _process
ERROR:HDLCompiler:806 - "D:/dss/ef.vhd" Line 80: Syntax error near "<".
ERROR:HDLCompiler:488 - "D:/dss/ef.vhd" Line 81: Illegal identifier : _period
ERROR:HDLCompiler:488 - "D:/dss/ef.vhd" Line 83: Illegal identifier : _period
WARNING:HDLCompiler:1369 - "D:/dss/ef.vhd" Line 78: Possible infinite loop; process does not have a wait statement
ERROR:HDLCompiler:806 - "D:/dss/ef.vhd" Line 93: Syntax error near "<".
ERROR:HDLCompiler:488 - "D:/dss/ef.vhd" Line 93: Illegal identifier : _period
WARNING:HDLCompiler:1369 - "D:/dss/ef.vhd" Line 88: Possible infinite loop; process does not have a wait statement
ERROR:HDLCompiler:854 - "D:/dss/ef.vhd" Line 38: Unit <behavior> ignored due to previous errors.
VHDL file D:/dss/ef.vhd ignored due to errors

Process "Simulate Behavioral Model" failed

 

[FvM]

You might have noticed that <clock> is a placeholder you must replace with a legal VHDL name...

 

[jacksparrow93]

hey i did it by changing <clock> to co (thank you!) now in Stimulus process i need to put zeroes or ones to signals to see simulation. Can someone expain how does it work?

this is now example of it

 

[ads-ee]

hey i did it by changing <clock> to co (thank you!) now in Stimulus process i need to put zeroes or ones to signals to see simulation. Can someone expain how does it work?

this is now example of it
View attachment 135783

Huh? are you asking how do you write stimulus vectors to your DUT?

-- in the most primitive bit banging method...
sig1 <= '1';
sig2 <= '0';
--...etc...
wait for 100 ns;
sig1 <= '0';
sig2 <= '1';
wait for 20 ns;
--...etc...

If you want a more sophisticated approach then you can use procedures and BFMs to drive the DUT.