Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
use a wr__rd_b select to decide which operation you are doing (can be a simple wr__rd_b <= ~wr__rd_b; toggle if you can tolerate it being free running). Verilog or VHDL has nothing to do with the problem, you need to design the circuit to do this function first. Translating it to Verilog (or VHDL) is the easy part.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.