ngtdat
Newbie level 3
Hi all,
I just made a vhdl code for my 7-segment decoders and here is my code:
when i complied the code, it seemed OK but when i put it in model sim and simulate, the results are not as i expect
can anyone tell me what i was wrong
I just made a vhdl code for my 7-segment decoders and here is my code:
Code:
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
entity char_seg7 is
port(a,b,c,d: in std_logic;
hex: out std_logic_vector(0 to 6));
end char_seg7;
architecture char_seg7 of char_seg7 is
begin
process (a,b,c,d)
begin
case "abcd" is
when "0000" => hex <= "0000001";
when "0001" => hex <= "1001111";
when "0010" => hex <= "0010010";
when "0011" => hex <= "0000110";
when "0100" => hex <= "1001100";
when "0101" => hex <= "0100100";
when "0110" => hex <= "0100000";
when "0111" => hex <= "0001111";
when "1000" => hex <= "0000000";
when "1001" => hex <= "0000100";
when others => hex <= "1111111";
end case;
end process;
end char_seg7;
when i complied the code, it seemed OK but when i put it in model sim and simulate, the results are not as i expect
can anyone tell me what i was wrong