sispyhus
Newbie level 2
some problems with VHDL.I have checked it for many times,but Quartus always report the mistakes.i would appreciate it if you can help me.
the code as follows:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity score is
port(load:in std_logic;
clk,up,dn,en1,en2:in std_logic;
scorein:in std_logic_vector(3 downto 0);
scoreoutut std_logic_vector(3 downto 0));
end score;
architecture behave of score is
begin
process(load,clk)
variable temp:std_logic_vector(3 downto 0);
begin
temp:=scorein;
if load='1' then........................................................18
temp:="0101";
elsif clk'event and clk='1' then....................................20
if up='1' and en1='1' and en2='1' then
if temp="1001" then
null;
else
temp:=temp+1;
end if;
elsif dn='1' and en1='1' and en2='1' then
if temp="0000" then
null;
else
temp:=temp-1;
end if;
end if;
end if;
scoreout<=temp;
end process;
end behave;
..........................................................
the mistakes :
Error (10818): Netlist error at SCORE.vhd(18): can't infer register for temp[0] because it does not hold its value outside the clock edge
Error (10818): Netlist error at SCORE.vhd(18): can't infer register for temp[1] because it does not hold its value outside the clock edge
Error (10818): Netlist error at SCORE.vhd(18): can't infer register for temp[2] because it does not hold its value outside the clock edge
Error (10818): Netlist error at SCORE.vhd(18): can't infer register for temp[3] because it does not hold its value outside the clock edge
Error (10822): HDL error at SCORE.vhd(20): couldn't implement registers for assignments on this clock edge
Error: Can't elaborate user hierarchy "score4:45|SCORE:1"
the code as follows:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity score is
port(load:in std_logic;
clk,up,dn,en1,en2:in std_logic;
scorein:in std_logic_vector(3 downto 0);
scoreoutut std_logic_vector(3 downto 0));
end score;
architecture behave of score is
begin
process(load,clk)
variable temp:std_logic_vector(3 downto 0);
begin
temp:=scorein;
if load='1' then........................................................18
temp:="0101";
elsif clk'event and clk='1' then....................................20
if up='1' and en1='1' and en2='1' then
if temp="1001" then
null;
else
temp:=temp+1;
end if;
elsif dn='1' and en1='1' and en2='1' then
if temp="0000" then
null;
else
temp:=temp-1;
end if;
end if;
end if;
scoreout<=temp;
end process;
end behave;
..........................................................
the mistakes :
Error (10818): Netlist error at SCORE.vhd(18): can't infer register for temp[0] because it does not hold its value outside the clock edge
Error (10818): Netlist error at SCORE.vhd(18): can't infer register for temp[1] because it does not hold its value outside the clock edge
Error (10818): Netlist error at SCORE.vhd(18): can't infer register for temp[2] because it does not hold its value outside the clock edge
Error (10818): Netlist error at SCORE.vhd(18): can't infer register for temp[3] because it does not hold its value outside the clock edge
Error (10822): HDL error at SCORE.vhd(20): couldn't implement registers for assignments on this clock edge
Error: Can't elaborate user hierarchy "score4:45|SCORE:1"