Iuri
Member level 2
I'm beginner at VHDL and I was trying to implement a 4 bits Register, but I have no idea of how to do it. The code below is what I got at this moment:
Please, someone can set me a direction?
thank you very much!
Code:
library ieee;
use ieee.std_logic_1164.all;
entity Register4Bits is
port ( D0, D1, D2, D3 : inout std_logic;
WR : in std_logic ); -- W = 0 , R = 1
end Register4Bits;
architecture archRegister4Bits of Register4Bits is
begin
WriteRead : process ( WR )
begin
if WR'event and WR = '1' then
elsif WR'event and WR = '0' then
end if;
end process;
end archRegister4Bits;
Please, someone can set me a direction?
thank you very much!