Help me with synthesis problems of a Verilog code

[nirav1983]

device utilization

Hi, I am new to verilog design.
I have made a 53 bit carry lookahead adder which is part of my floating point adder project. The simulation is perfect but I get a synthesis report

Device utilization summary:
---------------------------

Selected Device : 2s100tq144-6

Number of Slices: 110 out of 1200 9%
Number of 4 input LUTs: 191 out of 2400 7%
Number of bonded IOBs: 161 out of 96 167% (*)

WARNING:Xst:1336 - (*) More than 100% of Device resources are used
This is for a
Target Device : xc2s100-6-tq144


What are these IOBs and how can i minimise the count.

I am also attaching my verilog code .........

Also please suggest some reading on FPGA schematics so i can understand them better

 

[llrry]

Synthesis Help

Hi, I think you can download a spec of xc2s100 in Xilinx web site, which will make you understood on the internal resource of an FPGA.

 

[Git]

Re: Synthesis Help

Bonded IOBs are Input Output Buffers, ie actual pins on the chip. The chip you chose has 144 pins but only 96 are available for your I/O and you are trying to use 161 pins for I/O. 53 A inputs, 53 B inputs and 53 adder outputs, plus clock and carry?

Git

 

[nirav1983]

Synthesis Help

Hi guys, another problem
i designed a counter as a latch and an adder ...like

always @ (posedge clk)
q <=d;
assign d = q + 1;
assign clk = main_clk & ~terminal_count;
assign terminal_count = |d;

suppose i have a 2 bit counter.....then in an actual working, i would have the counter terminating one clock edge after the d turns 11 because of the time delay involved in getting d......but in a normal simulation run, i get it as terminating exactly on d = 11. How do i simulate but taking the timing specs into account.

 

[shengkaiyi]

Re: Synthesis Help

Your code seems have some problem because you want to control the clk by terminal_count signal. I think the following code will be more reasonable:

reg [1:0] q;

always @(posedge main_clk) begin
if (q != 2'b11) begin
q <= #1 (q+1);
end
end

 

[nirav1983]

Re: Synthesis Help

Hi,
Thanks for helping out guys.
I have managed to rectify the clock problem.

I wanted to know more about what JTAG and the Boundary scan mode are.

 

[eda_wiz]

Synthesis Help

https://www.ti.com/sc/docs/jtag/seminar1.pdf
https://www.ti.com/sc/docs/jtag/seminar2.pdf

 

[silver_kiss]

Re: Synthesis Help

read this might be helpfull for u