Help me with my VHDL code for a pulse generator

[ZeleC]

pulse width generator in vhdl

im trying to do a pulse generator to be implemented in a cpld
the idea is to get an output pulse of 280 us derived from a 25khz clock
the pulse starts on rising edge of trig
i wrote this and it worked as expecteted when i simulated in modelsim
entity timer280us is
Port ( Clk25k : in std_logic;
Trig : in std_logic;
Output : out std_logic);
end timer280us;

architecture Behavioral of timer280us is
signal counter : std_logic_vector(2 downto 0) := "000";
signal Timer_on : std_logic := '0' ;
signal output_temp : std_logic := '1';
begin
countrocess (Clk25k,Trig)
begin
if trig = '1' then
-- if Timer_On = '1' then
counter <= "000";
Timer_on <= '1';
-- end if ;
elsif Clk25k'event and (Clk25k = '1') then
if Timer_On = '1' then
counter <= counter + 1;
Output_temp <= '0';
if counter = "110" then
Timer_On <= '0';
Output_temp <= '1';

end if ;
end if ;
end if ;
end process;

--resetrocess(trig)
--begin
-- if rising_edge(trig) then
-- counter <= "000";
-- Timer_On <= '1';

-- end if;
--end process;
output <= output_temp ;


end Behavioral;

but the problem was that when a trigger pulse occured and as long as the trig = '1' the counter would not start , what i want to do is to start immediately on the rising edge of trig
so how can i rewrite my code so to do this.

 

[yerics]

vhdl Q?

I think you can do it just change "If trig=1" then to "If trog=0"
do you think so?

 

[r_e_m_y]

Re: vhdl Q?

try this :
entity timer280us is
Port ( Clk25k : in std_logic;
reset : in std_logic;
trig : in std_logic;
Output : out std_logic);
end timer280us;

architecture Behavioral of timer280us is
signal counter : unsigned(2 downto 0);
signal delay_Trig : std_logic;
signal output_temp : std_logic;
begin
count: process(Clk25k,reset)
begin
if reset = '1' then
counter <= "000";
delay_trig <= '0';
Output_temp <= '1';
elsif Clk25k'event and (Clk25k = '1') then
delay_trig <= trig;
if ((trig = '1') and (delay_trig = '0')) or ((counter > 0) and (counter < 7)) then
counter <= counter + 1;
Output_temp <= '0';
else
counter <= "000";
Output_temp <= '1';
end if;
end if;
end process;
output <= output_temp;
end Behavioral;
:wink:

 

[ZeleC]

Re: vhdl Q?

thx a lot remy
and i changed the code a little by removing reset
the result was as i wanted , but please read my q? at the end
my code
entity Timer280us is
Port ( Clk25k : in std_logic;
Trig : in std_logic:='0';
-- reset : in std_logic;
Output : out std_logic:='1');
end Timer280us;



architecture Behavioral of timer280us is
signal counter : unsigned(2 downto 0);
signal delay_Trig : std_logic;
signal output_temp : std_logic;
begin
count: process(Clk25k)
begin
-- if reset = '1' then
-- counter <= "000";
-- delay_trig <= '0';
-- Output_temp <= '1';
if Clk25k'event and (Clk25k = '1') then
delay_trig <= trig;
if ((trig = '1') and (delay_trig = '0')) or ((counter > 0) and (counter < 7)) then
counter <= counter + 1;
Output_temp <= '0';
else
counter <= "000";
Output_temp <= '1';
end if;
end if;
end process;
output <= output_temp;

end Behavioral;


But there is one question i want to ask you , actually im just a vhdl beginer and im trying to learn by myself
I was trying to understand ur code especially the two line
delay_trig <= trig;
if ((trig = '1') and (delay_trig = '0')) or ((counter > 0) and (counter < 7)) then

how this condition will meet "(trig = '1') and (delay_trig = '0')" if always before ,delay_trig gets the value of trig; so if trig is 1 delay_trig is 1
and if 0 dlay trig is zero. i just want to know if im misunderstanding something . thx u again r_e_m_y

 

[r_e_m_y]

Re: vhdl Q?

Hi,

Do not ever forget that you are describing flip flop register and logic gate combinations when you write synthesisable vhdl.

When I write delay_trig <= trig, that means that i want the D input of my flip flop to be connected to the trig signal.
in a RTL view, you will have :
delay_trig.D <= trig
when I write if delay_trig ='0' and trig ='1', that means that i want to have the result of a AND gate with the Q output of the flip_flop and the trig signal.
in a RTL view, you will have :
if delay_trig.Q = '0' and trig = '1'

So, delay_trig, as it is said in its name, is the trig signal delayed by 1 clock cycle. on the rising edge of trig, trig = 1 but delay_trig is still not at '1'.
Do a post-layout simulation of this code to understand this.

And, by the way, you should keep a reset signal for your design...

 

[ZeleC]

vhdl Q?

thank you a lot r_e_m_y for your help maybe the problem is im not thinking RTL
Do you have a link or ebook that gives me a better understanding of how synthesisable vhdl works ?
thk u again

 

[ZeleC]

vhdl Q?

i found one thing that is wrong
if the pulse is smaller that Clk25k cycle it would not work so i added this and it worked

entity Timer280us is
Port ( Clk_40us : in std_logic;
Width_Trig : in std_logic:='0';
reset : in std_logic;
Pulse_End : out std_logic;
Pulse280us : out std_logic:='1');
end Timer280us;




architecture Behavioral of timer280us is
signal counter : unsigned(2 downto 0);
signal delay_Trig : std_logic ;
signal Pulse_End_Temp : std_logic;
signal temp : std_logic := '0' ;
signal output_temp : std_logic:='1';
begin
process(Clk_40us,reset)
begin
if reset = '0' then
counter <= "000";
delay_trig <= '0';
Output_temp <= '1';
temp <= '0';
elsif Width_Trig = '1' then
temp <= '1';
elsif Clk_40us'event and (Clk_40us = '1') then
delay_trig <= Width_Trig;
if ((Width_Trig = '1') and (delay_trig = '0')) or ((counter > 0) and (counter < 7)) or ((temp ='1') and (counter = "000")) then
counter <= counter + 1;
Output_temp <= '0';
Pulse_End_Temp <= '0';
else
counter <= "000";
Output_temp <= '1';
Pulse_End_Temp <= '1';
temp <= '0';
end if;
end if;
end process;
Pulse280us <= output_temp;
Pulse_End <= Pulse_End_Temp ;
end Behavioral;

 

[anee_anil]

Re: vhdl Q?

Hi all,

I'm trying to do a pulse generator to be implemented in a cpld
the idea is to get an output pulse derived from a 80Mhz clock.

The frequency of the output is derived by 16-bit data and a clock.
e.g., 0000000000000001 indicates 12.5ns output frequency
0000000000000010 indicates 25ns output frequency.

The pulse width of the output is derived by 10 bit data
e.g., 0000000001 indicates 12.5ns pulse width
0000000010 indicates 25ns pulse width

and there will be 6 bit input, through which we can select 8 output ports.
when we select other signal, the previous signal should retain the data.


entity pulse_gen is
port(clk : in std_logic;
freq_data : in std_logic_vector(15 downto 0);
pulse_width_data : in std_logic_vector(9 downto 0);
wave_sel : in std_logic_vector(5 downto 0);
out_wave : out std_logic_vector(7 downto 0));
end entity;