Help me out clearing this timing violation

[altair_06]

Hi ...

Can anyone help me out in clearing this timing violation. These are the violations i get when i run timing simulation.


Warning! Timing violation
$setuphold<setup>( posedge CLK:4758 PS, posedge CE &&& (ce_clk_enable != 0):4394 PS, 510 : 510 PS, -58 : -58 PS );
File: /workspace/tools/xilinx8.2i_lnx86/verilog/src/simprims/X_SFF.v, line = 89
Scope: test_sample_main.sample_main_u1.\sample_instance/h6[8]
Time: 4758 PS


Warning! Timing violation
$setuphold<setup>( posedge CLK:4761 PS, posedge CE &&& (ce_clk_enable != 0):4359 PS, 510 : 510 PS, -58 : -58 PS );
File: /workspace/tools/xilinx8.2i_lnx86/verilog/src/simprims/X_SFF.v, line = 89
Scope: test_sample_main.sample_main_u1.\sample_instance/h6[1]
Time: 4761 PS


Warning! Timing violation
$setuphold<setup>( posedge CLK:4761 PS, posedge CE &&& (ce_clk_enable != 0):4359 PS, 510 : 510 PS, -58 : -58 PS );
File: /workspace/tools/xilinx8.2i_lnx86/verilog/src/simprims/X_SFF.v, line = 89
Scope: test_sample_main.sample_main_u1.\sample_instance/h6[0]
Time: 4761 PS