Help me fix a VHDL syntax error

[mo.khairy.mo]

hi all
when i write this VHDL code

if ((a = 0) | (b = 0)) then
					
       c    <= (others=>'0');

end if;

i found this error

Syntax error near "|"

could anyone help me to fix this error

thanks in advance

 

[FvM]

VHDL syntax error

"|" isn't a defined standard VHDL operator. Did you mean "OR"?

 

[mo.khairy.mo]

VHDL syntax error

yeah i mean if either a=0 or b=0 and i don't want to check the result of a or b

 

[vipinlal]

Re: VHDL syntax error

Write the code like this :

if ((a = 0) or (b = 0)) then 
                
       c    <= (others=>'0'); 

end if;

--vipin
https://vhdlguru.blogspot.com/