alierossi
Newbie level 6
verilog problem..
can you correct my code... i dont how to use switch with the clock. so that when i on the swicth the clock start j is start counting. plez help me.
module counter(
output reg [7:0] keluar,
input clk,
input switch,
);
// reg [5:0] result = 6'b000000;
reg en = 1'b0;
reg [2:0]i = 0;
integer j= 0;
always @ ( posedge clk)
begin
j <= j + 1;
if (j == 13'd4999)
begin
en <= 1'b1;
j <= 0;
end
else
en <= 1'b0;
end
always @ ( posedge en )
begin
i <= i + 1;
end
always @ (clk,i)
begin
keluar <= 8'b00000000;
case (i)
0 : keluar <= 8'b00000000;
1 : keluar <= 8'b00000001;
2 : keluar <= 8'b00000100;
3 : keluar <= 8'b00001010;
4 : keluar <= 8'b00010010;
5 : keluar <= 8'b00100010;
6 : keluar <= 8'b01000010;
7 : keluar <= 8'b11000010;
default:keluar<=8'bzzzzzzzz;
endcase
//assign keluar = result;
end
endmodule
can you correct my code... i dont how to use switch with the clock. so that when i on the swicth the clock start j is start counting. plez help me.
module counter(
output reg [7:0] keluar,
input clk,
input switch,
);
// reg [5:0] result = 6'b000000;
reg en = 1'b0;
reg [2:0]i = 0;
integer j= 0;
always @ ( posedge clk)
begin
j <= j + 1;
if (j == 13'd4999)
begin
en <= 1'b1;
j <= 0;
end
else
en <= 1'b0;
end
always @ ( posedge en )
begin
i <= i + 1;
end
always @ (clk,i)
begin
keluar <= 8'b00000000;
case (i)
0 : keluar <= 8'b00000000;
1 : keluar <= 8'b00000001;
2 : keluar <= 8'b00000100;
3 : keluar <= 8'b00001010;
4 : keluar <= 8'b00010010;
5 : keluar <= 8'b00100010;
6 : keluar <= 8'b01000010;
7 : keluar <= 8'b11000010;
default:keluar<=8'bzzzzzzzz;
endcase
//assign keluar = result;
end
endmodule