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Your first image is actually a resistive voltage divider followed by voltage follower, this technique is often preferred over the use of a simple resistive voltage divider when the output is feed to an ADC.
The reasoning is the added output impedance due to the resistive network of the voltage divider, the total resistance must be high enough to sufficiently limit current flow, while maintaining a low enough output impedance (source resistance) to prevent improper operation/transfer to the ADC stage.
The voltage follower overcomes these limitations by providing a very low output impedance (source resistance), even with a relatively high input impedance of a voltage divider.
Excess source resistance can serious impair the operation of an ADC, including the maximum sample rate and specified accuracy.
Recommend limits on source resistance largely depends on the ADC device and are usually addressed in its datasheet:
The analog inputs of the LTC1594/LTC1598 look like a
20pF capacitor (CIN) in series with a 500Ω resistor (RON)
and a 45Ω channel resistance as shown in Figure 8.
CIN gets switched between the selected “analog” and
“COM” inputs once during each conversion cycle. Large
external source resistors and capacitances will slow the
settling of the inputs. It is important that the overall RC
time constants be short enough to allow the analog
inputs to completely settle within the allowed time.
When driving the analog inputs with an op amp it is
important that the op amp settle within the allowed time
(see Figure 7). Again, the “analog” and “COM” input
sampling times can be extended as described above to
accommodate slower op amps. Most op amps, including
the LT®1006 and LT1413 single supply op amps, can be
made to settle well even with the minimum settling
windows of 4.8μs (“analog” input) which occur at the
maximum clock rate of 320kHz.
The right side circuit with the resistive network connected to the negative input of the opamp is an amplifier so I can't see how you intend to use it for attenuation, the min gain is 1.
I think a resistive divider would work fine, just add a capacitor across the ADC input so that the S&H circuit sees a low impedance instead of the higher resistance of the divider but this will have some effect on the speed of the input so if your signal is changing fast then it may be better to use the divider followed by the opamp buffer.
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