[SOLVED] What type of voltage source that generate a sequence of binary that I can set for example like [1, 0, 0, 1, 1] sequence.

Hi what kind of voltage source that generate a sequence of binary. Like other voltage source generate square wave we call that Vpulse, Vdc to generate dc signal, Vpwl for generating piecewise linear signal. In my case I want to generate a sequence of binary wave and it is not random. Signal that I set myself.

 

[FvM]

You are asking about simulation or real hardware? In the latter case, what is voltage, current, pulse width? Repeated sequence or single shot?

 

[D.A.(Tony)Stewart]

Any CMOS logic chip has a driver with an effective series resistance Vol/Io=Zo and some capacitive load and thus has some finite risetime which is said to be "piecewise linear signal". If the output resistance was <=0 then this would not be true.

Then you simply define your parameters for data pattern , speed and logic thresholds or use the datasheet standard values for latency (delay) and generate your pattern however you choose.

e.g. PISO Shift register, parallel in , Serial clocked data out.
Load any patterns you choose. If using some protocol like NRZ, Bi-phase or PWM then adjust design accordingly.

All "real" voltage sources & all drivers also have some series resistance. Even if the risetime is nonlinear, it is still PWL due to the RC effects. If your simulator has a logic or analog driver with 0 output impedance like Falstad's and ideal capacitors with 0 ESR and you put them in parallel, you will get a violation error so some ESR must be added to create a current limit, then with practical load capacitance and/or induction of the path, create a PWL signal. This is useful to know why CMOS drivers have a standardized RdsOn or Zo with tolerances for some voltage drop at a standard test current. They are still voltage sources and also have some standard resistance with wide tolerances like 25% or so to create PWL signals in logic with specified loads and rise times.

What is an example of a voltage source that is not PWL?

If you used a dry contact switch after the source to drive any load then open the switch, in theory it would be infinite voltage from the finite load inductance and thus not PWL. Thus you must limit the risetime with some resistive load or clamp the voltage with controlled resistance.

Generating a pattern is a separate issue. This is opposite what you wanted, a random sequence but shows the effect of a non-PWL voltage source with 0 ohms and a dry switch.

Is this too much info?

 

[BradtheRad]

4017 IC (1-thru-10 counter) produces a sequence of highs or lows as programmed by the user.

 

[dick_freebird]

For brief sequences a stack of pulsed sources, each RZ, with proper
nonoverlap phasing is simple and you could make each one's
"happy time" a variable or a vector(bit). You could make this arbitraratily
long using iterated instances / busses wrapped, in a CAD environment
that keeps track correctly of such things, at pretty low effort.

For extremely long sequences I ended up at veriloga sources made
from VCD files that were given to me, through a series of sed scripts
(later on one of the CAD ladies made me some Perl scripts that did
the same).

Since some simulators have nice veriloga interfaces and some not-so,
I'd recommend seeing where the "source rack" approach gets you.

 

[D.A.(Tony)Stewart]

4017 IC (1-thru-10 counter) produces a sequence of highs or lows as programmed by the user.

This replicates your specified pattern exactly and ought to be the accepted answer.

 

[danadakk]

Sequence of 64 bits -

64 bit Shift Register Single Chip

Occasionally I need long shift registers. This is a design done on a single PSOC chip using verilog. Its 64 bits wide, SIPO, with controls to clear or set all bits. Notice many additional chip resources went un used that are availble for other tasks, like COM, Timer, Counter, Analog,.....see...

www.edaboard.com

If you need to do this at different voltage level for a specfic burst easy to do with
same part using one of its onboard DACs.


Regards, Dana.