Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Opamp -1 and +1 stable

yefj

Advanced Member level 4
Joined
Sep 12, 2019
Messages
1,195
Helped
1
Reputation
2
Reaction score
3
Trophy points
38
Activity points
7,217
Hello, What is the meaning of gain -1 stable, gain of +1 stable for an opamp as shown below?
Does it somehow says that the input signal to the opamp needs to connect on plus or minus to the opamp so it will be stable?
Thanks.
 
No in short, its a measure of stability due to gain and phase, and usually C loading, sometimes even
fdbk network stray C at summing junction.

OpAmp Stability :





There is literally 10's of thousands of books and papers and ap notes on this topic, youtube (analog devices has
a series of videos).....


Regards, Dana.
 
Hello Dana , in a data sheet they present an opamp datasheet as a pair of model is 1 stable while the other is -1 stable.
So when I handle these pairs how do distinguish the way I need to handle each one ?
If you could show an example of 1 stable.

Thanks .
 
Last edited:
Normally +1 stable infers a voltage follower, - 1 a unity gain inverter configuration.

Look at page 14 for a discussion.

Follower -

1707750840618.png


-1 Gain inverter (both R's equal) -

1707750922334.png


Regards, Dana.
 
Hello Dana , so lt1028 is more suitable in inverter follower configuration .
If I put it into voltage follower configuration it will become unstable ?
Thanks .
 
Page 14 discusses how to do +1 G.

Always read a datasheets app section, as well as specs. Will keep you out of trouble.

Regards, Dana.
 
Normally +1 stable infers a voltage follower, - 1 a unity gain inverter configuration.

Explanation:
1.) For a non-inverting amplifier with a closed-loop gain Acl=+1 the loop gain is identical to the opamps open-loop gain Aol (very large)
2.) For an inverting amplifier with Acl=-1 the loop gain is identical to Aol/2 (Ao-3 db).

Both cases represent the most critical application as far as stability is concerned (maximum feedback).
(However, one should note that, in practice, both cases do not differ because the open-loop gain has much more tolerances than 3dB)
 
Hello,i put LT1128 into -1 stable configuration, however i dont see this opamp going unstable.
i dont see the opamp going unstable :)
where am i going wrong in testing stability of LT1128 stability +1?
Thanks.
1708092381797.png
 
Hello,i put LT1128 into -1 stable configuration, however i dont see this opamp going unstable.
i dont see the opamp going unstable :)
where am i going wrong in testing stability of LT1128 stability +1?
Where are you gong wrong? --> in your assumption.

Why do you expect it to be unstable?

Klaus

added:
* If you want to test +1 stability, then use a circuit with gain of +1.

* The shown circuit isn´t even gain of -1 it rather is a gain of -300.

What are you doing? and why?
What are you expecting? and why?
 
Hello Klaus, I understand my error, i have made a plus 1 stable opamp of non inverting configuration.
I have made the following configuration as you can see i get a barchausen instability.
but its not stable far away at 115.6MHz.
Is the a way i could put a filter to eliminitate osciltions?
Thanks.
1708095007463.png

1708095073355.png
 
Depends on how good a job they did on spice model. If you look at their discussion page 15 in datasheet
on stability seems to have a lot to do with 50 ohm environment. Seems like they do not discuss
C loading on output. However if you look at these :

1708095322730.png


you can see at very light Cload phase margin issues creeping in. So I think spice model
needs some more complete implementation.

I did see this :

1708095636708.png


So above 100 pF overshoot (read phase margin) causing concern.

My experience is fats OpAmps are a real serious challenge, especially to prototype and keep
stable. Even Ceramic C's for bypass, one vendor to another, dame value, quite different in
effectiveness. Lead / trace L defintely channlenge. Normally in datasheet there are bypassing
recomendations, seems like this one no. Shame.

For ref :

1708095943853.png


I think above os for a dominant two pole system. Stray C's easily add more poles to the 2-3 already present in a fast OpAmp.


Regards, Dana.
 
Last edited:
Hello Klaus, I understand my error, i have made a plus 1 stable opamp of non inverting configuration.
I have made the following configuration as you can see i get a barchausen instability.
but its not stable far away at 115.6MHz.
Is the a way i could put a filter to eliminitate osciltions?
Thanks.
1) It seems that you have applied a stabiliy criterion on the closed-loop gain response. That is not correct.
Instead, the well-known stability criteria are based on the loop gain - that is the gain of the complete loop when it is broken at a sitable node.
(By the way: A "Barkhausen instability" criterion does not exist. There is only a criterion from Barkhausen called "condition for oscillation")

2) Please note that a closed loop circuit can be either stable or unstable.
That means: We cannot say that a circuit will be "not stable far away at 115.6 MHz". There will be not such a frequency limit.

3) In your diagrams, the gain and phase response looks quite normal for a stable opamp based non-inverting gain stage.
 
Last edited:
Hi,

post#13:

this is not gain of +1, your circuit is gain of +51.

"not stable far away at 115.6 MHz" --> makes not much sense for an OPAMP with a GBW of 13MHz

Klaus
 
Hello Dana,i am trying to undesrand the article you posted and simulate it in LTSPICE.
What is the meaning of applying AC at some node and simultanisly measuring the node.
So we will measure the stimuluse signal :)
given the circuit below could you please say how it putting stimulus and measuring the same node in LTSPICE?


1708100232207.png

1708100303330.png
 
I am not a LTC user, or rather I avoid it whenever possible.

Take a look at these two videos :

Pick watch on youtube



Regards, Dana.
--- Updated ---

Depends on how good a job they did on spice model. If you look at their discussion page 15 in datasheet
on stability seems to have a lot to do with 50 ohm environment. Seems like they do not discuss
C loading on output. However if you look at these :

View attachment 188662

you can see at very light Cload phase margin issues creeping in. So I think spice model
needs some more complete implementation.

I did see this :

View attachment 188663

So above 100 pF overshoot (read phase margin) causing concern.

My experience is fats OpAmps are a real serious challenge, especially to prototype and keep
stable. Even Ceramic C's for bypass, one vendor to another, dame value, quite different in
effectiveness. Lead / trace L defintely channlenge. Normally in datasheet there are bypassing
recomendations, seems like this one no. Shame.

For ref :

View attachment 188664

I think above os for a dominant two pole system. Stray C's easily add more poles to the 2-3 already present in a fast OpAmp.


Regards, Dana.
Would love to correct spelling on this but editing is terminated in nS
on this site, post #14 ?
 

    yefj

    Points: 2
    Helpful Answer Positive Rating
You dont have to break the loop to do stability analysis :


And Middlebrook :



Regards, Dana.
The following comment is intended to avoid confusing the questioner with the different terminology and to clear up any misunderstandings.

1) The best-known stability criterion is that of H. Nyquist, which consists of feeding a test signal into the feedback loop, which must be broken for this purpose.
The evaluation of the loop gain (magnitude and phase) then enables a statement to be made about the stability of the closed loop - and also about the degree of stability (phase margin).

2) The method described in the first linked article by Dana allows (a) only a statement like "stable yes/no" and (b) just an approximate statement (under certain simplifying assumptions) about the phase margin (evaluation of the step response overshoot ).

3) The second article (Middlebrook) describes the classic method for simulating the loop gain (see 1), whereby for opamp applications the test voltage can be injected BETWEEN the two nodes created during opening the loop (while maintaining the DC operating point).

That means: The loop remains closed for DC, but acts as an open loop for ac signals, otherwise it would not be possible to determine the gain of the loop (output-to-input ratio).

I hope this comment could clarify some things.

At this point, I would like to mention that there is a relatively new method for the exact determination of the phase margin, in which the feedback loop can really be regarded as still closed:
 
Last edited:
  • Like
Reactions: yefj

    yefj

    Points: 2
    Helpful Answer Positive Rating

LaTeX Commands Quick-Menu:

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top