Help: Error in my VHDL Code(Working with arrays)

[amisin]

I am new to VHDL programming, and I have written this code:

---

Code VHDL - [expand]
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--------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
--------------------------------------------------------
 
entity imagebin2dnastream is
 
generic(RR,CC: INTEGER := 2);
port(Input: IN std_logic;
  Output: OUT std_logic
);
 
end imagebin2dnastream;
 
--------------------------------------------------------
 
architecture behaviorb2d of imagebin2dnastream is
 
type type_binaryin is array (0 to 1) of std_logic_vector(31 downto 0); 
 
signal loopcount : integer;
signal dnacount : integer := 0;
signal binaryin : type_binaryin;
signal dnaout: string(1 to 16);
signal store: std_logic_vector(31 downto 0);
 
begin
 
store <= binaryin(0);
  process(Input)
    begin
  for loopcount in 0 to 31 loop
    if (store(loopcount,loopcount + 1) = '00') then
      dna(dnacount) <= 'A';
    elsif (store(loopcount,loopcount + 1) = '01') then
      dna(dnacount) <= 'T';
    elsif (store(loopcount,loopcount + 1) = '10') then
      dna(dnacount) <= 'C';
    else (store(loopcount,loopcount + 1) = '11') then
      dna(dnacount) <= 'G';
  end if
  loopcount := loopcount + 1;
  dnacount <= dnacount + 1;
end loop;
end process;
end behaviorb2d;
 
--------------------------------------------------------

---

And I am getting the error: imagebin2dnastream.vhd(39): near "'": syntax error, in line (if (store(loopcount,loopcount + 1) = '00') then
)

 

[FvM]

To fix the obvious syntax error, you need to use correct syntax for std_logic_vector constants. It's "01" in contrast to '0' for bits.

At second sight, there are more errors, that will either cause failure in simulation/compilation or prevent the design to work as expected. Without claiming completeness:
- index store(loopcount,loopcount + 1) is out of range for loopcount = 31
- dnacount <= dnacount + 1; doesn't assign a new value during for loop evaluation. Please review your VHDL text book for the difference between signal and variable behaviour.

 

[amisin]

Thanks FvM,
I have corrected the code as:
CODE VHDL:

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Code VHDL - [expand]
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--------------------------------------------------------
--------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--------------------------------------------------------
entity imagebin2dnastream is
generic(RR,CC: INTEGER := 2);
port(Input: IN std_logic;
  Output: OUT std_logic
);
end imagebin2dnastream;
--------------------------------------------------------
architecture behaviorb2d of imagebin2dnastream is
 
type type_binaryin is array (0 to 1) of std_logic_vector(0 to 31); 
-- signal loopcount : integer;
signal dnacount : integer := 0;
signal binaryin : type_binaryin;
signal dnaout: string(1 to 16);
signal store: std_logic_vector(0 to 31);
begin
binaryin(0) <= "00100101101010101101011101011010";
store <= binaryin(0);
  process(Input)
    variable loopcount: integer := 0;
  begin
  for loopcount in 0 to 30 loop
    if (store(loopcount) = '0') then
      if (store(loopcount+1) = '0') then
      dnaout(dnacount) <= 'A';
      elsif (store(loopcount) = '1') then
      dnaout(dnacount) <= 'T';
      end if;
    elsif (store(loopcount) = '1') then
      if (store(loopcount+1) = '0') then
      dnaout(dnacount) <= 'C';
      elsif (store(loopcount) = '1') then
      dnaout(dnacount) <= 'G';
      end if;
    end if;
  loopcount <= loopcount + 1;
  dnacount <= dnacount + 1;
end loop;
end process;
end architecture behaviorb2d;
--------------------------------------------------------
--------------------------------------------------------

---

I am using dnacount to increment the value value to dnaout index, where I am saving the DNA codes.
Still I am getting some errors regarding, variable assignment. Error: Target of signal assignment is not a signal in line (loopcount <= loopcount + 1
Can you help?

 

[FvM]

I am using dnacount to increment the value value to dnaout index

So you didn't yet find time to read about variables and signals in a process? :sad:

Still I am getting some errors regarding, variable assignment. Error: Target of signal assignment is not a signal in line (loopcount <= loopcount + 1

Yes, loopcount := loopcount + 1; has been already wrong in the first code (I overlooked the point) and loopcount <= loopcount + 1; is as well. loopcount is already the name of the loop variable. It's implicitely defined with the loop statement and automatically incremented. It must not conflict with an existing signal name.

There are several necessary comments related to dnacount.
- to be incremented during loop evaluation, as apparently intended, it must be defined as a variable inside the process
- it must be initialized
- you need to assure that the dna index keeps the range

As an additional comment, the discussed design part isn't connected to input or output signals. Thus it will be removed in design synthesis.