Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
What is this HUE metric of which you speak, I can only find it referenced here: https://ieeexplore.ieee.org/document/5118242/
The way it is talked about here, it is not a factor of hardware utilization, but more about how well the design is pipelined - ie. how many idle cycles compared to active cycles.
This is something that will be design dependent and depend on many factors, and will only be calculated by the user through theory or from experimentation.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.