FSM design using 3 process

[graphene]

Hi,
I am designing an FSM for my project. I am from SW background but new to VHDL and Xilinx.

1) I have a counter with just CLOCK, and RESET inputs and a OUTPUT
2) I have a PISO with RESET, CLOCK, PARALLEL DATA and LOAD inputs and SERIAL OUTPUT.

I now need to create an FSM that controls how the 2 components (Counter and PISO) are controlled.

The problem is despite any eforrts the output when IN_COUNT, IN_LOW_SYNC are asserted doesnt impact on my simulation results.

Can you help me with this. And also any tutorial on how to frame a BUBBLE DIAGRAM for MEALY state machines will be very helpful to me.
The code for the FSM is given below

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;


entity fsm_for_dac is
	port(
		IN_CLK		: in STD_LOGIC;
		IN_RST		: in STD_LOGIC;
		IN_COUNT	        : in STD_LOGIC; -- logic 1 or 0 that disables or enables count respectively
		IN_LOW_SYNC	: in STD_LOGIC;
		-- general outputs
		OUT_RST 	: out STD_LOGIC; -- common output for both PISO AND Counter
		-- output to PISO
		OUT_SYNC 	: out STD_LOGIC; -- SYNC output to the PISO
		OUT_LOAD 	: out STD_LOGIC; -- LOAD that enables the PISO
		OUT_DATA 	: out STD_LOGIC -- PARALLEL DATA to the PISO
	);
end fsm_for_dac;

architecture Behavioral of fsm_for_dac is

	type fsm_state is (state_reset, state_sync, state_piso); 
	signal present_state, next_state : fsm_state;
	
begin
	
	clk_process: process (IN_CLK)
	begin
			if (rising_edge(IN_CLK)) then
				if (IN_RST='1') then
					present_state <= state_reset;
				else 
					present_state <= next_state;
				end if;
			end if;
	end process clk_process;
	
	
	next_state_process: process(present_state, IN_RST,IN_LOW_SYNC, IN_COUNT) --
		begin
			case present_state is
			
				when state_reset => 
					if (IN_RST='1') then 
						next_state <= state_reset; -- it remains on the same reset state
					else
						next_state <= state_sync; -- if IN_LOW_SYNC is '0',  then piso operation starts
					end if;
					
				when state_sync =>
					if (IN_RST='1') then 
						next_state <= state_reset; 
					elsif (IN_COUNT='0') then 
						next_state <= state_piso;    
					else
						next_state <= state_sync; 
					end if;
						
				when state_piso =>
					if (IN_RST='1') then 
						next_state <= state_reset; 
					elsif (IN_COUNT='0') then 
						next_state <= state_piso; -- if IN_LOW_SYNC is '0',  then piso operation 
					else
						next_state <= state_reset; 
					end if;

			end case;
					
	end process next_state_process;
		
	output_process: process(present_state, IN_RST, IN_COUNT)
	begin
		case present_state is

			when state_reset => 
					OUT_RST <= '1';
					OUT_SYNC <= '1';
					OUT_DATA <= '0';
					OUT_LOAD <= '0';
					
			-- when state_sync =>
					-- OUT_RST <= '0';
					-- OUT_SYNC <= '0';
					-- OUT_DATA <= '1';
					-- OUT_DATA <= '0';
				
			when state_piso =>
					OUT_RST <= '0';
					OUT_SYNC <= '0';
					OUT_DATA <= '1';
					OUT_LOAD <= '1';
					
								
			when others => 
					OUT_RST <= '1';
					OUT_SYNC <= '1';
					OUT_DATA <= '0';
					OUT_DATA <= '0';
					OUT_LOAD <= '0';
		
		end case;
		
	end process output_process;
	
	
end Behavioral;

 

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There shouldn't be a reset in the next state transition process as it's not a clocked process and does not represent flip-flops. Your reset is already included in clk_process.

You aren't even using the signal IN_LOW_SYNC in the next_state_process, and your comments about IN_LOW_SYNC make no sense as you aren't even looking at IN_LOW_SYNC.

You have OUT_DATA repeated in the others clause of the output_process.


Regards

 

[graphene]

Thank you friend...

I dint not understand about the RESET in the transition. Can you please explain me once again.

1) The remaining I have corrected.Pleas let me know that. Thanks in advance.

2) Also another basic question. Can a state diagram have multiple inputs from nowhere ?? I guess the answer is Yes , but how to construct such a diagram. Can you suggest me in text how many states and transition can this have ?

In the Fig. below, a) the floating input to the FSM in the diagram is to be ignored, b) the floating input in ORANGE line can be ignored. The final output from the DAC will be analog voltage so that can also be ignored. This is what I could draw quickly in word, please excuse guys..

 

[FvM]

A state diagram is a graphic representation of a finite state machine. It has usually one and only one "input from nowhere", the transition to the initial respectively reset state. I don't see what should be the meaning of multiple transitions from the outside?

 

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  when state_reset => 
    if (IN_RST='1') then 
      next_state <= state_reset; -- it remains on the same reset state
    else
      next_state <= state_sync; -- if IN_LOW_SYNC is '0',  then piso operation starts
    end if;

This is what I meant, IN_RST should not be used in the combinational state transistion process (the process called next_state_process). This process doesn't represent registers, it represents the combinational logic that feeds the registers. This is also where you have a problem with IN_LOW_SYNC not being used.

I think you should have written something like the following:

  when state_reset => 
    if (IN_LOW_SYNC='1') then 
      next_state <= state_reset; -- it remains on the same reset state (This is the IDLE state)
    else
      next_state <= state_sync; -- if IN_LOW_SYNC is '0',  then piso operation starts
    end if;

If you have a SW background you should know how to draw a bubble diagram of a FSM, as FSMs are also used in software.

Regards