File i/o problem in verilog

[adivy]

I am able to read only the first line in input text file .Can anyone please help me out in debugging this code
In1 and In2 are 32 bit register values and AE is 1 bit binary value.Read is a task inside the testbench which uses file inputs .Code is:

---

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file=$fopen("input.txt","r");
                
                while (!$feof(file) )
                  @(posedge MCLK)
                 begin
                 
                 ret = $fscanf(file,"%h%h%b \n",in1,in2,AE);
                 read(in1,in2,AE);
                end
                $fclose(file);

---

Input txt file is:
FFFFFF FFFFFF 1
FAFAFA FAFAFA 1
000000 AAAAAA 1

 

[poluekt]

You can add $display("in1=%h in2=%h AE=%b",in1,in2,AE); after ret = $fscanf(file,"%h%h%b \n",in1,in2,AE); for results displaying.

 

[adivy]

You can add $display("in1=%h in2=%h AE=%b",in1,in2,AE); after ret = $fscanf(file,"%h%h%b \n",in1,in2,AE); for results displaying.

But my problem is I am not able to read the next two lines in text file into in1,in2 and AE.

 

[mrflibble]

Works just fine over here.

Of course you did not specify the magic ingredient... What is the magic ingredient you ask?

Well, in what blocks you are running your code snippet of course.

So basically the tip is to please next time just paste the entire code. Because as it is I can grab your code and then make two pieces of sort of reasonable looking verilog. One will not do what you want, and the other does do what you want. And they both are 100% consistent with your code fragment.

Anyways, this quick quick test works (in the sense that it reads all lines).

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module tb_omgwtfbbq;
 
    reg MCLK=0;
    integer file;
    integer ret;
    integer in1, in2, AE;
 
initial begin
    file=$fopen("input.txt", "r");
                
//     $fclose(file);
end
 
 
always begin
    # 10 MCLK <= ~MCLK;
end
 
always begin
     while (!$feof(file) ) begin
         @(posedge MCLK)
         begin
             ret = $fscanf(file,"%h%h%b \n", in1, in2, AE);
             $display("%h ... %h ... %b XXX\n", in1, in2, AE);
//             read(in1,in2,AE);
         end
     end
 
end
endmodule

---

Not the prettiest code ever, but I was lazy + curious. Lazy so this is it. And curious as in you had me wondering what could possibly go wrong. What most probably went wrong is you did everything in the initial block or something?

 

[adivy]

You are write .It is the problem with initial block.I replaced the function and put it inside always block .Still I have a problem.
My task read starts like this :


task read(input [23:0] Data1,Data2);
begin
Dataout_reg1<=Data1;
Dataout_reg2<=Data2;
....
end
endtask;

It is basically a BFM.The Data1 and Data2 are the values read in in1 and in2.Now the problem is the registers inside the task are getting update whenever there is change in in1 and in2.Is it the problem the way I am calling the task.
I call the task only once in:
always @(MCLK)
begin
#100 read(in1,in2);

end

---------- Post added at 19:30 ---------- Previous post was at 19:29 ----------

Sorry I meant right not write

 

[mrflibble]

Luckily you maintain your high standards of not including full code. There is something to be said for being consistent. I guess you'll just have to wait until someone that likes guessing reads your post!

If you don't want to wait how about cultivating the habit of including the entire code?

---------- Post added at 15:05 ---------- Previous post was at 15:03 ----------

To be clear: by entire code I mean the entire module. So that I can cut and paste it into the simulator here, press GO, and watch the output. Otherwise far too much room for making the wrong assumptions.

 

[adivy]

Sorry I thought no one would be interested in going through the whole code.Now I understood writing the whole code only makes sense. New to posting questions thats why.
Code is:

---

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`timescale 1 ns / 1 ps
 
 module adc_bfm;
          
//Inputs
reg MCLK,RESET_N,SYNC_N;
reg  FSI_N,SDI;
reg adc_en;
 
//Outputs
wire SDO,SCO,FSO_N;                           
 
//Parameter Declaration
parameter clock_period=6'd25; 
parameter DEC_RATE=2'b01;            //64x Decimation rate
parameter FS=1'b0,OVR=1'b0,LPWR=1'b0;
 
//Signals
reg [7:0] Status_reg ;
reg [23:0] Dataout_reg1 ,in1;
reg [23:0] Dataout_reg2,in2 ;
reg [15:0] Reg_addin1;
reg [15:0] Reg_addin2;
reg [15:0] Datain_reg1;
reg [15:0] Datain_reg2;
reg SDO_i;
reg FSO_Ni;
reg SCO_i;
reg AE;
 
integer i;
integer file,ret;
 
initial 
begin
 
// Default values of inputs
 
MCLK<=1'b0;
SCO_i<=1'b0;
RESET_N<=1'b1;
SYNC_N<=1'b1;
FSI_N<=1'b1;
SDI<=1'b0;
SDO_i <=1'b0;
FSO_Ni<= 1'b1;
//adc_en=1'b1;
AE<=1'b0;
 
                Status_reg<={FS,OVR,LPWR,DEC_RATE,3'b000};
                 Dataout_reg1<=24'd0;
                 Dataout_reg2<=24'd0;
                 in1<=24'd0;
                 in2<=24'd0;
                 Dataout_reg2<=24'd0;
                 Datain_reg1<=24'd0;
                 Datain_reg2<=24'd0;
                 SDO_i <=1'b0;
                 FSO_Ni<= 1'b1;
    
                file=$fopen("input.txt","r");
                
                while (!$feof(file) )
                  @(posedge MCLK)
                 begin
                 ret = $fscanf(file,"%h %h %b",in1,in2,AE);
                 #500 $display("in1=%h in2=%h AE=%b",in1,in2,AE);
                 
                 
                end
                
                $fclose(file);    
    
 
end 
 
 
  always  #(clock_period/2.0)  MCLK=~MCLK ;               
  always  #(clock_period/4.0)  SCO_i<=~SCO_i;
  
  always @(MCLK)
  begin
 #100 read(in1,in2,AE);
 
  end
 
task read(input [23:0] Data1,Data2,
                input AE);
begin
Dataout_reg1<=Data1;
Dataout_reg2<=Data2;
adc_en<=AE;
 
 @(negedge MCLK)
    if (adc_en==1 )
        begin
           RESET_N<=1'b1;
          @(negedge MCLK) 
            RESET_N<=1'b0;
             @(negedge MCLK)
                RESET_N<=1'b1;
             @(negedge MCLK)
             @(negedge MCLK)      
             @(posedge MCLK)
                SYNC_N<=1'b0;        
             # (4*clock_period)
                SYNC_N<=1'b1;     
                
 
        while (adc_en==1)
                begin
                
                    @(posedge SCO_i) 
                    #1 FSO_Ni<= 1'b0;
                    #10 SDO_i<=Dataout_reg1[23];
                    for (i=0;i<23;i=i+1)
                    begin
                        @(posedge SCO_i)
                            SDO_i<=Dataout_reg1[22-i];
                    end
                    for (i=0;i<8;i=i+1)
                    begin
                        @(posedge SCO_i)
                            SDO_i<=Status_reg[7-i];
                    end 
                    
                    #2 FSO_Ni<= 1'b1;
                    
                    for (i=0;i<24;i=i+1)
                    begin
                        @(posedge SCO_i)
                            SDO_i<=Dataout_reg2[23-i];
                    end
                    for (i=0;i<8;i=i+1)
                    begin
                        @(posedge SCO_i)
                            SDO_i<=Status_reg[7-i];
                    end 
 
                end
 
end
  else
       begin        
       FSO_Ni<= 1'b1;
       end
end
endtask
 
assign SDO = SDO_i;
assign FSO_N = FSO_Ni;
assign SCO= adc_en?SCO_i:0;
 
  endmodule

---

 

[mrflibble]

Sorry I thought no one would be interested in going through the whole code.Now I understood writing the whole code only makes sense. New to posting questions thats why.
Code is:

You guess correctly. I am not interested in going through the whole code. By contrast I am even far less interested in having to guess what all you might be using that results in your "it doesn't do what I want".

So I shall not read all your code because who cares. I shall however cut & paste it unread into the simulator, press GO, and then see if I can duplicate your problem.

So no problem.

Oh yeah, psst, don't let Alex read this.

See this bit:

---------- Post added at 15:47 ---------- Previous post was at 15:38 ----------

Right. Simulated it. And indeed, only the first line.

And it is because of exactly the same reason as your first post.

You do this bit:

                while (!$feof(file) )
                  @(posedge MCLK)
                 begin
                 ret = $fscanf(file,"%h %h %b",in1,in2,AE);
                 #500 $display("in1=%h in2=%h AE=%b",in1,in2,AE);

INSIDE of the "initial" block. That is all cool, but it will not give you the endresult you unreasonably expect.

The initial block is evaluated BEFORE the clock starts running so to speak. So you can @posedge MCLK all you want, but there are no posedges to be had at this point in time. And as such not much will happen.

So take that out of the initial block as in my previous example and you'll be fine.