Fifo depth and fifo pointers

[karthik87]

Hi

I am using an asynchronous FIFO in my UART design and my data width is 32 bits wide.pl tel me how to calculate the width and depth of the FIFO
Also pl explain me how the FULL and EMPTY conditions are met.
as i am using two different clocks for writing and reading pl tel me how to synchronize both of them.

Thanks in advance

 

[ali_umair21]

You can use synchronizer circuits to sync read and write pointers, these are usually simple series of flops(usually 2 flops). To measure depth of a cyclic buffer or FIFO you can refer wikipedia for upto four techniques through which you can measure depth or FULL and EMPTY conditions. You can also use megawizard for Altera and coregen for xilinx, to create a FIFO of your choice.

 

[Brownout]

An asynchronous fifo, also refered to a synchronizing fifo, does not requre synchronizer circuits. The fifo has two different clock domains, and all the synchronizing circuits are integrated. To use it, simply connect the interface signals from each clock domain to the two ports. The FULL signal is asserted when all the addresses of the fifo has data which has not yet been read, EMPTY means either no data has been written, or else all written data has been read.

 

[sakshi gupta]

Can somebody elaborate more on this ?

 

[mrflibble]

Can somebody elaborate more on this ?

Can you please be more specific?

 

[sakshi gupta]

can you please update what should be full & empty conditions of fifo ?

sakshi

 

[elec4fun]

It depends of the ability of source/sink to put/get data from the FIFO fast enough.

For exemple, let's say you have an UART feeding a FIFO on one side and, on the other side a driver which is wake up when FIFO is "almost full".
If your "almost full" level is to high, may be your driver won't have time to handle the interrupt before the UART fill the remaining space of the FIFO.

This is an interresting link : Calculating FIFO Depth

Regards,
Franck.