FIFO and Serial Transmitter in VHDL

[Morell]

Hi Guys

I need your help again.

Here is the Scenario of what I want to do :

1- I have and input that is std_logic_vector (N downto 0) and 5<N<31.
N is a Generic.

2- I want to send this input (5 to 31 bits) with my serial transmitter.

I am going to Discribe that I plan to do, if u have any suggestion, tips advices and etc
please reply to this thread.


My Plan :

1- I set the Transmitter as the top module, so from now on, everything happens in the transmitter.

2- In this module , I have a state machine. At first I would convert this string to bytes.
I have a component called Str2Bytes(). In the first state I use the output of this component.
Let's assume that the component works perfectly (I didn't design it yet).

For example : N is equal to 18. We pass 18 bits to Str2Bytes() and it gives us Three Bytes.
First byte : Output_byte_Reg(2) = (23 downto 16) = 000000XX (The only bits that we need
are the two right bits).
Second byte : Output_byte_Reg(1) = (15 downto 0)
Third Byte : Output_byte_Reg(0) = The least significant 8 bits (7 downto 0)

3- When Str2Bytes() finished (For example with a flag named Finished_Reg) then we go to the
next state. This state is called Set_Data. In this state we put one of those Output_byte_Reg(i)
in another signal (Data_Out_Reg). Data_Out_Reg is the signal that is sent bit by bit.
Now we go to the next state (Transmit).

4- In this state, we send the data bit by bit (This part is designed and implemented on the board
and worked). After that we go back to Set_Data state and read the next byte until the all the
bytes have been sent.

So right now i think that the Str2Byte() should do the FIFO job too. But i have no idea how to synchronize Str2Byte() with the top module (Transmitter).For example how can I tell the Str2Bytes() to give me the next byte or how can I find out that all the bytes have been sent and the
Str2Bytes() (Which is also a FIFO too) is empty and so on. Basically I don't now how to control this component with the top module.


1- If you think my plan has a problem please tell me and give me your suggestion pleas.
2- If you think it is right, just tell me what should i design first? (Str2Bytes , Transmitter?)
and what are the control signals? and the inputs and outputs that is necessary for these modules.

Right now I am trying to write what I've just Discribed and I will post the codes a.s.a.p.


I would greatly appreciate it if you kindly give me some advices on this research.

Thanks alot.

 

[TrickyDicky]

FIFOs usually have control signals:
Write side:
full and enable

Read side:
empty and enable

With these 4 signals, you can tell if there is a word in the FIFO and enable the next one on/out of the FIFO.

 

[ads-ee]

1- I have and input that is std_logic_vector (N downto 0) and 5<N<31.
N is a Generic.

2- I want to send this input (5 to 31 bits) with my serial transmitter.

What is the lower range? (4 downto 0) 5-bits? or (6 downto 0) 5<N<31?

Doesn't really matter with how you implement this, but engineering is all about the details. If you don't keep the details straight you end up with planes with wings that fall off, ICs that release magic smoke, iphones with batteries that get overcharged, etc.

Previously you have stated that you are trying to send between 1 to 4 bytes to a serial transmitter.

Use a shift register, or more useful a double buffered shift register, one parallel register for up to a 4 byte input (gives you more timing leeway for loading the parallel data), a second shift register that has a parallel load (from the first register) to serially shift out the bytes. You would also need to give the number of bytes to send and load the shift register with data justified with the direction of the shift. e.g.

input bytes and number of bytes to send (3)
xx b1 b2 b3 3
< shift direction

load shift register
b1 b2 b3 xx
< shift MSB first

Depending on the rest of the requirements, you may or may not need a FIFO to buffer data to handle input data burst conditions.

By the way, translating software concepts to hardware usually ends up making hardware designs that are overly complicated, perform poorly, use excessive resources, and are generally just bad. It's obvious there is a software programming bias given the fact you are thinking of the data as strings which you convert to byte (char type data).