rayhh27
Member level 1
Hi, I am looking around and I found this code from VHDLguru website. I see a type which is i am not familiar with which is record. Can anyone explain to me in a simple manner about what is record in this code mean?
The code is in this website. https://vhdlguru.blogspot.co.id/2011/06/non-synthesisable-vhdl-code-for-8-point.html
The author said that it is not synthesizeable, may I know what does it mean by not synthesizeable?
Does it mean that it is still simulateable? or it is just some algorithm to describe the design flow?
Second question, in this example he write sum.r, may I know what does this mean? Does it say that sum will be type r?
What I do not understand is that despite it said that it is complex in the record r and i both declared to be real?
Thanks a lot. And yes I am a completely newbie who wants to learn so please be patient with me. Thank you.
The code is in this website. https://vhdlguru.blogspot.co.id/2011/06/non-synthesisable-vhdl-code-for-8-point.html
The author said that it is not synthesizeable, may I know what does it mean by not synthesizeable?
Does it mean that it is still simulateable? or it is just some algorithm to describe the design flow?
Code VHDL - [expand] 1 2 3 4 5 type complex is record r : real; i : real; end record;
Second question, in this example he write sum.r, may I know what does this mean? Does it say that sum will be type r?
What I do not understand is that despite it said that it is complex in the record r and i both declared to be real?
Code VHDL - [expand] 1 2 3 4 begin sum.r:=n1.r + n2.r; sum.i:=n1.i + n2.i; return sum;
Thanks a lot. And yes I am a completely newbie who wants to learn so please be patient with me. Thank you.
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