Fault analysis for CMOS Fabrication

[020170]

Hello.

During Fabrication Fault Analysis, I found metal short or open issue.



this picture shows top metal lines short.



This picture shows metal line open

In my opinion, it looks fabrication issue. because metal line's width is 0.8um, and space is not minimum.

max current is 110uA through opened metal line. current value is not large, current density issue can not be happened.

How about your opinion these issues?

thanks

 

[erikl]

The top metal shorts could have been created by the cross-section grinding.

The metal line open could be over-current (ESD ?) ... or fab issue (dust). Always at the same position?

 

[dick_freebird]

The same-position question is key to resolving whether
these are random litho, or on-mask defects.

I can't see why those "stringers" would be where they
are and so consistently, in fabrication. Normally an
etch failure would leave residual metal at the bottom,
not halfway up. Is there a multi-step interlevel dielectric
involved, or is flat-field ILD thickness half of the metal
height? What does anything like SIMS say about
composition of this "feature"?