error,in vhdl code,sr latch..cannot solve 1! help !

[rambleach]

library ieee;
use ieee.std_logic_1164.all;


-- it is basically nand based sbar Rbar latch
entity sr_latch is
  port (S,R:in std_logic;Q,Qbar : out std_logic);
end entity sr_latch;

architecture exm1 of sr_latch is
  begin
    prc:process (R,S) 
    begin
      case std_logic_vector(R,S) is
      when "00"=>
        Q<='1';
        Qbar<='1';
    when "01"=>
    Q<= '1';
    Qbar<='0';
    
  when "10"=>
  Q<='0';
  Qbar<='1';
  
when others=>
null;
end case;
end process prc;
end architecture exm1;

these are the errors:
** Error: C:/Modeltech_pe_edu_10.1a/examples/sr latch.vhd(14): Type conversion (to STD_LOGIC_VECTOR) can not have aggregate operand.
** Error: C:/Modeltech_pe_edu_10.1a/examples/sr latch.vhd(30): VHDL Compiler exiting

 

[K-J]

Your use of 'std_logic_vector(R,S) is that of a function that receives two input parameters. But 'std_logic_vector' is a type, therefore 'std_logic_vector(...)' would be a type conversion which makes your usage invalid.

What you want to do is basically concatenate R and S together to create a std_logic_vector. If you were to do this...
case R & S is
you would find that the expression 'R & S' has two interpretations and is therefore ambiguous so the compiler would complain. So what you need to do here is explicitly tell the compiler the type that is intended like this...
case std_logic_vector'(R & S) is

Note the tick mark after the 'std_logic_vector'. That is called a type qualifier and is used in cases like this where you need to have a specific type, but what you have has more than one interpretation.

Another example would be...
"10"...is this a std_logic_vector, a std_ulogic_vector, a bit_vector or a string? Can't tell, so if the compiler complains about an ambiguous type you would again use the tick mark
string'("10") -- example, here to indicate that "10" is meant to be interpreted as a string

Kevin Jennings

 

[rambleach]

okay K-J i did what you suggested, and it worked..Now the compiler says

Compile of sr latch.vhd was successful with warnings.

and the warnings are:

** Warning: C:/Modeltech_pe_edu_10.1a/examples/sr latch.vhd(14): (vcom-1186) Array type case expression must be of a locally static subtype.

 

[K-J]

okay K-J i did what you suggested, and it worked..Now the compiler says

Compile of sr latch.vhd was successful with warnings.

and the warnings are:

** Warning: C:/Modeltech_pe_edu_10.1a/examples/sr latch.vhd(14): (vcom-1186) Array type case expression must be of a locally static subtype.

That's because case expressions must be static and functions potentially are not. The way to fix the warning is to come up with a local variable that is the concatenation of the two bits as shown in the code below. Note that now, because the result of the concatenation is being assigned to a std_logic_vector variable, the result of 'R & S' is no longer ambiguous so you technically don't need to do the type qualifier tick mark. Either of the two assignments to 'RS' will work, pick which one you prefer.

---

Code VHDL - [expand]
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prc:process (R,S) 
      variable RS: std_logic_vector(1 downto 0);
    begin
      RS := std_logic_vector'(R & S);  -- This will work
      RS := R & S;  -- And so will this, because now the compiler knows that the left hand side is a std_logic_vector so the result is not ambiguous
      case RS is

---

Kevin Jennings