rambleach
Junior Member level 1
Code:
library ieee;
use ieee.std_logic_1164.all;
-- it is basically nand based sbar Rbar latch
entity sr_latch is
port (S,R:in std_logic;Q,Qbar : out std_logic);
end entity sr_latch;
architecture exm1 of sr_latch is
begin
prc:process (R,S)
begin
case std_logic_vector(R,S) is
when "00"=>
Q<='1';
Qbar<='1';
when "01"=>
Q<= '1';
Qbar<='0';
when "10"=>
Q<='0';
Qbar<='1';
when others=>
null;
end case;
end process prc;
end architecture exm1;
these are the errors:
** Error: C:/Modeltech_pe_edu_10.1a/examples/sr latch.vhd(14): Type conversion (to STD_LOGIC_VECTOR) can not have aggregate operand.
** Error: C:/Modeltech_pe_edu_10.1a/examples/sr latch.vhd(30): VHDL Compiler exiting