Error : "Cannot connect a VHDL scalar signal to Verilog vector port" in Modelsim

[Cesar0182]

Greetings, let you know that I have found an example of an asynchronous fifo in verilog and I have implemented it to my vhdl project in Vivado 20192.2 but I am having problems trying to simulate it in Modelsim SE 10.5. I am getting the following error from the image.


Could someone help me with this problem please, I leave part of the fifo code and how I am trying to implement it in my project.

FIFO Code:

`timescale 1ns / 1ps

module l1_spi_async_fifo_slv#(
    parameter DATA_WIDTH = 1,
    parameter DATA_DEPTH = 1024
    )(
    input wr_clk,
    input wr_rst,
    input wr_en,
    input [DATA_WIDTH - 1 : 0] wr_data,
    output reg full,

    input rd_clk,
    input rd_rst,
    input rd_en,
    output reg [DATA_WIDTH - 1 : 0] rd_data,
    output reg empty

    );

Main code:

slv_mosi_miso_ff_arst                        : std_logic;
spi_clk_syn                                    : std_logic;
tx_byte_to_bit                                : std_logic;
tx_bit_length_wr                            : std_logic;
fifo_rd_bits_en                                : std_logic;
signal rd_data_slv_f1                       : std_logic;
signal empty_slv_f1                         : std_logic;
signal full_slv_f1                          : std_logic;

u_spi_async_fifo_slv_f1 : entity work.l1_spi_async_fifo_slv
    generic map(
    DATA_WIDTH => 1,
    DATA_DEPTH => 1024)
  PORT MAP(
    wr_rst      => slv_mosi_miso_ff_arst,
    rd_rst      => slv_mosi_miso_ff_arst,
    wr_clk      => i_clk_25Mhz,
    rd_clk      => spi_clk_syn,
    wr_data     => tx_byte_to_bit,
    wr_en       => tx_bit_length_wr,
    rd_en       => fifo_rd_bits_en,
    rd_data     => rd_data_slv_f1,
    full        => full_slv_f1,
    empty       => empty_slv_f1
  );

 

[FlyingDutch]

Greetings, let you know that I have found an example of an asynchronous fifo in verilog and I have implemented it to my vhdl project in Vivado 20192.2 but I am having problems trying to simulate it in Modelsim SE 10.5. I am getting the following error from the image.

View attachment 172431
Could someone help me with this problem please, I leave part of the fifo code and how I am trying to implement it in my project.

FIFO Code:

`timescale 1ns / 1ps

module l1_spi_async_fifo_slv#(
    parameter DATA_WIDTH = 1,
    parameter DATA_DEPTH = 1024
    )(
    input wr_clk,
    input wr_rst,
    input wr_en,
    input [DATA_WIDTH - 1 : 0] wr_data,
    output reg full,

    input rd_clk,
    input rd_rst,
    input rd_en,
    output reg [DATA_WIDTH - 1 : 0] rd_data,
    output reg empty

    );

Main code:

slv_mosi_miso_ff_arst                        : std_logic;
spi_clk_syn                                    : std_logic;
tx_byte_to_bit                                : std_logic;
tx_bit_length_wr                            : std_logic;
fifo_rd_bits_en                                : std_logic;
signal rd_data_slv_f1                       : std_logic;
signal empty_slv_f1                         : std_logic;
signal full_slv_f1                          : std_logic;

u_spi_async_fifo_slv_f1 : entity work.l1_spi_async_fifo_slv
    generic map(
    DATA_WIDTH => 1,
    DATA_DEPTH => 1024)
  PORT MAP(
    wr_rst      => slv_mosi_miso_ff_arst,
    rd_rst      => slv_mosi_miso_ff_arst,
    wr_clk      => i_clk_25Mhz,
    rd_clk      => spi_clk_syn,
    wr_data     => tx_byte_to_bit,
    wr_en       => tx_bit_length_wr,
    rd_en       => fifo_rd_bits_en,
    rd_data     => rd_data_slv_f1,
    full        => full_slv_f1,
    empty       => empty_slv_f1
  );

Hello,

the error message is clear: you are trying in your code to assign scalar data to vector data. More precisely you have:
1) output reg [DATA_WIDTH - 1 : 0] rd_data, (which is vector)
and signal
2) signal rd_data_slv_f1 : std_logic; (which is scalasr)

and then in line: rd_data => rd_data_slv_f1,

you are assign this scalar signal to register which is vector.

Best Regards

 

[FvM]

You want to connect std_logic_vector signals of correct size.

 

[Cesar0182]

Hola

el mensaje de error es claro: está intentando en su código asignar datos escalares a datos vectoriales. Más precisamente tienes:
1) salida reg [DATA_WIDTH - 1 : 0] rd_data, (que es vector)
y señal
2) rd_data_slv_f1 de señal: std_logic; (que es scalasr)

y luego en línea: rd_data => rd_data_slv_f1,

se le asigna esta señal escalar para registrar cuál es vector.

Saludos

gracias por la ayuda, acabo de resolver el error modificando la siguiente línea
[CÓDIGO]rd_data_slv_f1 de señal : std_logic_vector(0 hasta 0); [/CÓDIGO]

--- Updated Oct 20, 2021 ---

Hello,

the error message is clear: you are trying in your code to assign scalar data to vector data. More precisely you have:
1) output reg [DATA_WIDTH - 1 : 0] rd_data, (which is vector)
and signal
2) signal rd_data_slv_f1 : std_logic; (which is scalasr)

and then in line: rd_data => rd_data_slv_f1,

you are assign this scalar signal to register which is vector.

Best Regards

thanks for the help, I just solved the error by modifying the following line.

signal rd_data_slv_f1                       : std_logic_vector(0 downto 0);

 

[dpaul]

If the problem exists no more then please mark the thread as "Solved".