enhance Rds of a NMOS transistor

[perado]

which schematic is true? please mark positive and negative pin of Op-amp.
dgnani what you mean level68!?

 

[dgnani]

which schematic is true? please mark positive and negative pin of Op-amp.
dgnani what you mean level68!?

The correct schematic is the one posted by FvM (his experience level on this forum is marked as 68 -see side panel by his posts)
The drain goes to the inverting input of the opamp because you need negative feedback (for OP stability) and the FET in its feedback loop is operating as a source follower (or common drain or constant current mode, however you want to look at it) so it does not invert small signals from the FET gate

 

[leo_o2]

Yes, FvM is correct. Sorry for mistake.

 

[perado]

Is it a circuit schematic like that I want?? https://www.edaboard.com/threads/215720/

for small signal analysis what model I must replace instead of Op-amp?

 

[leo_o2]

Yes. It is a simply implementation. For Op model, you can just use a voltage controlled voltage source(vo=-vi.A).

 

[dgnani]

Is it a circuit schematic like that I want?? https://www.edaboard.com/threads/215720/

for small signal analysis what model I must replace instead of Op-amp?

the link you posted is always a regulated cascode but of course there is no opamp in there

if you want to regulate your cascode using an opamp like in post #19, then you can model it with either a
- vccs + parallel inpedance
- vcvs + series impedance

Using a vccs is closer to implementation because the transconductance of the vccs is simply the gm of your input pair, using a vcvs is somewhat more abstract and simpler. Add one or more poles by cascading RC filters