sambhav007
Junior Member level 1
Hi,
I am using Encounter RC compiler to synthesize my verilog/vhdl files into gate-level netlists, using a standard cell library.
However, the logic synthesis process only creates a synthesized .v file (output file)
Is it possible to generate a .vhd synthesized file using RTL compiler?
Thanks,
Sambhav
I am using Encounter RC compiler to synthesize my verilog/vhdl files into gate-level netlists, using a standard cell library.
However, the logic synthesis process only creates a synthesized .v file (output file)
Is it possible to generate a .vhd synthesized file using RTL compiler?
Thanks,
Sambhav