Effect of W < L for a MOSFET in layout and later stages

[Blackuni]

Hi,

Does any 1 came across any issues when using W < L for a mosfet, especially layout, fabrication related?

Thanks,

 

[keith1200rs]

W<L is occasionally used and doesn't present a problem provided it is within the process design rules. A bandgap startup circuit is one example where W<L is often used.

Keith

 

[refugee]

May be you should specify your problem. I dont think there arent any problem for w<l misfit itself.

 

[palmeiras]

There is no problem about it. Maybe you can think that the layout of such transistor would be weird, but it is normal.
For instance, Transistors operating in linear mode acts as resistors, and you can have W < L, in order to increase the resistance.

 

[Blackuni]

Thanks every 1,

Here is the root, I tried 2 design a simple CS amp with 100nA current using 180nm process and land up in W<L

Any pointer for very low (<100nA) design will be much helpfull.

Thanks,

 

[Blackuni]

Hi All,

To add to my problem, I have binning based mos model, the max. L & W is around 20u and 100u. my calculations results in device with size w/l as 6u/300u, up to my understanding, the models will be accurate only in the binning rage, how to handle this??

Thanks,

 

[palmeiras]

Hi Blackuni, What is your load? Passive, active load, diode connected?

 

[Blackuni]

Active load

 

[ic98]

why problem? you draw a MOSFET layout with a desired channel aspect ratio

 

[dinesh hegde]

I do not know if there any problems realted to fabrication.
But if we think of analog application where mismatch is critical thing then, yes
"Mismatch is less if W/L ratio is less"

You can refer to paper "Optimizing MOS Transistor Mismatch" by Simon J. Lovett, Marco Welten, Alan Mathewson, and Barry Mason.

 

[erikl]

I have binning based mos model, the max. L & W is around 20u and 100u. my calculations results in device with size w/l as 6u/300u, up to my understanding, the models will be accurate only in the binning rage, how to handle this??

You could stack 15 FETs with L=20µ serially, all bulks connected, all gates connected. Because of differences in the bulk control it's not identical to a single FET, but at least you can simulate it.