YangZ
Newbie level 5
Hey guys i need some advice. For the VHDL process statement shown below, if if_else statement A condition is fulfilled, will it continue to check the conditions of if_else statement B and C or exit the process and wait for the next clock cycle to execute if_else statement B and C??
Hope you guyz can give me some advice.Thank you!
Regards,
Yangz
process(clk,Reset,Enable1,Enable2)
begin
if rising_edge(clk) then
if Reset ='1' then
presentstate <= stidle; --if_else statement A
else
presentstate <= nextstate;
end if;
if Enable1 = '1' then
Delay <= Delay +'1'; --if_else statement B
elsif Enable1 = '0' then
Delay <= (others=>'0');
end if;
if Enable2 = '1' then
Counter <= Counter +'1';
elsif Enable2 = '0' then --if_else statement C
Counter <= (others=>'0');
end if;
end if;
end process;
Hope you guyz can give me some advice.Thank you!
Regards,
Yangz
process(clk,Reset,Enable1,Enable2)
begin
if rising_edge(clk) then
if Reset ='1' then
presentstate <= stidle; --if_else statement A
else
presentstate <= nextstate;
end if;
if Enable1 = '1' then
Delay <= Delay +'1'; --if_else statement B
elsif Enable1 = '0' then
Delay <= (others=>'0');
end if;
if Enable2 = '1' then
Counter <= Counter +'1';
elsif Enable2 = '0' then --if_else statement C
Counter <= (others=>'0');
end if;
end if;
end process;