Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Doubts in VHDL process statement

Status
Not open for further replies.

YangZ

Newbie level 5
Joined
Dec 4, 2009
Messages
9
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Location
Malaysia
Activity points
1,352
Hey guys i need some advice. For the VHDL process statement shown below, if if_else statement A condition is fulfilled, will it continue to check the conditions of if_else statement B and C or exit the process and wait for the next clock cycle to execute if_else statement B and C??

Hope you guyz can give me some advice.Thank you!

Regards,
Yangz

process(clk,Reset,Enable1,Enable2)
begin
if rising_edge(clk) then
if Reset ='1' then
presentstate <= stidle; --if_else statement A
else
presentstate <= nextstate;
end if;

if Enable1 = '1' then
Delay <= Delay +'1'; --if_else statement B
elsif Enable1 = '0' then
Delay <= (others=>'0');
end if;

if Enable2 = '1' then
Counter <= Counter +'1';
elsif Enable2 = '0' then --if_else statement C
Counter <= (others=>'0');
end if;
end if;
end process;
 

These are 3 independent statements, you will have each of them handled separately. If I was you, I would rather create 3 different process for each to make it easier to debug and simulate.
 

These three statements are totally incorrelated. Yes, the first, second and third if_else will always be processed all together.
 

yes your code will work perfectly on rising edge of clock it will check for conditions of all three A, B and C statements in parallel
and it will create 3 reg for presentstate, delay and counter.

but as farhada suggested it is always better to use different process for all 3 and...

specially one more suggestion probably here you need not to put reset, enable1 and enable2 in sensitivity list as the process is not sensitive to these signals it is just sensitive to clock and every thing will be executed at rising edge of clock only...

hope you got it clearly...

Added after 2 minutes:






all 3 statements will be executed in all clock cycles...

it will not wait any where for next clock cycle as above two guys mention there is no relation between A, B and C statements...

hope you are more clear about issue now...
 

Thanks for your advices and help. Yes it did clear my doubts!
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top