ASIC_intl
Banned
difference between reg and wire in verilog
What are the differences betwwen net (e.g. wire) and register in verilog. I know that register can store the value until or unless another value replaces them. But net also has same property.
Is the following syntax acceptable inside a verilog module?
wire a;
initial
begin
a = 1'b0;
end
What are the differences betwwen net (e.g. wire) and register in verilog. I know that register can store the value until or unless another value replaces them. But net also has same property.
Is the following syntax acceptable inside a verilog module?
wire a;
initial
begin
a = 1'b0;
end