difference between hold time and hold time margin

[deepa1206]

Hi

I understand what set-up and hold time is.
Are the terms hold time and hold time margin different? If so can anyone please explain or give some pointers? I searched the web but didnt get much info on what the term "hold time margin" is referring to.

Thanks

 

[ljxpjpjljx]

hold time margin is used for PT tools to set!

 

[deepa1206]

I didnt understand. What do you mean by used for PT tools to set!?

Suppose I am given a circuit which has some combinational logic between two flip flops. I am also give all necessary parameters like t(clock to Q), t(propagation delay) and so on, how do I determine hold time margin. As far as I know

thold < tcq + tpd_min

What is hold time margin here?

 

[rca]

the flop has a hold time constraints, and you can add some hold time margins. Then if the flop requires 500ps of hold time, you can add 100ps of margin, so the tool will fix (PR) and check (STA) that the minimum hold time is 600ps instead 500ps.

during the hold time fix step, you should drawn the figure hold time versus nbr of buffer added, and you can found the point where you add ennought margin without impacted the area, and by this way add some security margin to your design against OCV, voltage drop below the row....

 

[ljxpjpjljx]

in other words for easy understand, hold time margin is the extra time you set to make hold time more robust for your design!

 

[deepa1206]

Ok. So hold time margin is basically a cushion that you provide to your design so that your output instead of changing at t ns after the clock changes at t+x ns. This will help avoid hold time violations.

 

[ljxpjpjljx]

yes, you can understand it in this way!