diff b/w latchs and flipflop

[ankit12345]

diff b/w latchs and flipflop???

 

[aravind]

Latch is Level sensitive
FF is Edge sensitive
read any VLSI basic books.

 

[positive_edge]

JK Latches have the problem of race condition ( repeated toggling) during the '1' and '1' J , K input state state.

So this condition can be eliminated by using Flip Flops ( Master Slave Flip Flop)

Flip Flop -> Edge Sensitive

Latch -> Level Sensitive

Bye

 

[weng]

flip-flop passes the input when clock triggers (positive edge or negative edge)

latch passes the input when clock High (or Low)

 

[yuenkit]

the so-called "level sensitive" is it referring to the circuit which trigger at both posedge and negedge?

 

[stevepre]

No.

Only one. Otherwise, it's a buffer.

When level is high, latch gets whatever value coming in. When level is low, it won't latch new value (it stays at old value)

 

[elecs_gene]

hi guys,
could u guys tell me which part of the flip flop circuit makes it edge sensitive???see,if it is level triggered,then it is because of the and gate used,here in flip how is it made edge sensitive??

with regards

 

[sp]

to make it edge trigger... it use a method of master and slave... to be details.. search for master n slave FF...

regards,
sp

 

[alpeshchokshi]

hi
hey let me tell u one more thing

first differences
latch f/f
asynchronous block synchronous block

using feedback pair of same block of latch we
nand or nor it is made up use twice in master slave
so its a single block which consist configuration it becomes f/f
2 nand/nor in cross coupled so f/f consists 2 block of latch
feedback manner which is called first is master and second is slave
latch now slave latch decides either its
positive edge or negative.

its a level sensitive so o/p follows whereas ms f/f depend on the mode o
ip when enable which is asynchonous of operation edge will decide
ip is applied

hey this just the brief overview..
lot more concepts are there for this latch and f/f
i hv also some clear diagram will try to post it.
so that will give exact idea.

 

[r_p_sanna]

are there any design documents on asynchronous circuits ?

 

[p_shinde]

adding to the Q


which is more immune to noise , latch or ff?