Eli_221B
Newbie level 4
hello every one:wink: I have serious problems in writting vhdl structural 4 bit up/down binary counter code by 4 t flip flops.... this is my first code Im so confused and havent enough time. please help and guide me to learn and edit it . thank you so much
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 library ieee; use ieee.std_logic_1164.all; entity tff is port ( t :in std_logic; clock :in std_logic; reset :in std_logic; q :out std_logic ); end entity; architecture behavior of tff is signal s :std_logic; begin process (clock) begin if (clock'event and clock='1') then if (reset = '0') then s <= '0'; else s <= not s; end if; end if; end process; q <= s; end architecture; --------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity up_down_structure is port( up:in std_logic; down:in std_logic; clock:in std_logic; a0,a1,a2,a3:inout std_logic); end entity; architecture structural of up_down_structure is component tff is port( t: in std_logic; clock:in std_logic; q:out std_logic; qbar:inout std_logic); end component; signal t1,t2,t3,t4,t5,t6,t7,or_1,or_2,or_3,or_4,qbar1,qbar2,qbar3:std_logic; begin t1 <= ((not up) and down); t2 <= t1 and qbar1; t3 <= up and a0; t4 <= t2 and qbar2; t5 <= t3 and a1; t6 <= t4 and qbar3; t7 <= t5 and a2; or_1 <= up or t1; or_2 <= t2 or t3; or_3 <= t4 or t5; or_4 <= t6 or t7; t_ff1:tff port map(or_1 =>t,clock =>clock, q =>a0); t_ff2:tff port map(or_2 =>t,clock => clock,q =>a1); t_ff3:tff port map(or_3 =>t,clock => clock,q=>a2); t_ff4:tff port map(or_4 =>t,clock => clock,q =>a3); end architecture;
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