Decoupling and bulk capacitor

[dharithothi]

Hello Guys,

All says that Decoupling and bulk capacitors must be placed near to IC pin or beside of IC pin.
But it is not possible to put it all the time.
Placement and value of cap is dependent on current consumption of IC obviously.
But how far is good enough for capacitor placement???

 

[KlausST]

Hi,

The bulk capacitor is not that critical, you may use longer traces.

The high speed ceramics decoupling capacitor should be placed very close to the vcc pin.
But indeed it's not the trace length from vcc pin to capacitor only. Additionally the connection from capacitor to the GND plane is equally critical. Ground PLANE, not gnd traces.

And it's not the current consumption, but it's the rapid chane in VCC current. Short pulses are critical.
Imagine a microcontroller or PLD is switching 16 address lines and 8 data lines at the same time.
Lets say within 1ns from 0V to 3V, each line with only 7pF of capacity causes a short current pulse of about 0.5A.

Without the capacitor the voltage across the power traces may drop some 100mV ...causing malfunction of the device.
With a 100nF capacitor the voltage drop is less than 5mV, because the capacitor delivers the whole pulse energy.

Klaus

 

[dharithothi]

Hello KlausST,

Agreed, on your answer.

I am terminating Cap to GND plane and another terminal is connected to Vcc pin of IC by trace.
If I am not wrong ultimately inductance created by trace between cap and IC pin is going to create issue. I want to know about that distance. How much is critical.

Suppose for example
Cap's one terminal is on GND plane and another is 50 mil from Vcc pin of any IC. (just for example). I know in that if I am keeping 10mil trace width is better than 5mil of track width. But how can be I assure if I am keeping 10mil of width is ok for 50 mil of distance???

 

[KlausST]

Hi,

How much is critical.

...for a slow OPAMP maybe 10cm is enough.
...for a GHz switching IC every mm makes it worse.


Klaus

 

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Which is the reason there is a market for power integrity analysis being done on boards. Many PCB design houses now have people on staff that can do power integrity analysis on customer designs after the board layout is completed.

 

[Airbag79]

Hello KlausST,

Agreed, on your answer.

I am terminating Cap to GND plane and another terminal is connected to Vcc pin of IC by trace.
If I am not wrong ultimately inductance created by trace between cap and IC pin is going to create issue. I want to know about that distance. How much is critical.

Suppose for example
Cap's one terminal is on GND plane and another is 50 mil from Vcc pin of any IC. (just for example). I know in that if I am keeping 10mil trace width is better than 5mil of track width. But how can be I assure if I am keeping 10mil of width is ok for 50 mil of distance???

You first must determine what your target impedance is for your power rail. Let's say 100 mohms is the target impedance up to 150 MHz. You must then perform a Z parameter analysis (frequency domain) of the PWR/GND pair to understand the impedance profile over the frequency band of interest. Let's say DC - 150 MHz. From a lumped perspective, effective loop inductance is what drives excess and unwanted voltage ripple. Vrip = L*di/dt. It's imperative to reduce the effective loop inductance a given current loop sees. It also critical to identify any switching frequencies of interest along the impedance profile to understand if any modal peaks exist. If you have a critical clock switching at 100 MHz, and a corresponding modal peak at 2 ohms, your clock will most likelt will riddled with voltage ripple, and jitter.

First, determine what your peak transient current is for a given power/gnd pair you're going to analyze. Then determine you target impedance and perform a Z parameter analysis over the frequency band DC - 100 MHz. To calculate target impedance: Zt = (Vdd*allowable ripple in percent/I peak). So, for example, Let's say it's a 1.0 volta rail, with 3% allowable voltage ripple with a peak transient current (di/dt) of 2 AMPS. Plug in those numbers and your target impedance is 15 mohms

Z parameter (frequency domain analysis of your PWR/GND plane) is a good starting place.

Contrary to popular belief, XY location of capacitors is second order effect. First order effects are the loop inductance. Amount of L in the Z direction. Thinner PWR/GND spacing between layers is also a first order effect, which increase planar capacitance. Most ECAD tools allow you to run loop inductance reports for decoupling caps, typically 2nH and lower is desirable. for every cap you put down you get a 1/n reduction in L. But there are frequency limitations for decoupling caps as well.

 

[marce]

Get some power integrity software...