coding ....Design....errors in linting.....!

[rakesh_aadhimoolam]

Linting doubts :

1)what happens if reset is active high as well active low in same module.(reg are dependent on each other)

module lint_test(clock, reset);
input wire clock;
input wire reset;
reg [3:0] a;
reg [3:0] b;
always @(posedge clock or negedge reset)
if (reset)
a = 0;
else
a = a + 1;
always @(posedge clock)
if (!reset)
b = 0;
else
b = a;
endmodule

2)what happens if asynchronous as well synchronous reset are present in same block(reg are dependent on each other)

module lint_test(clock, reset);
input wire clock;
input wire reset;
reg [3:0] a;
reg [3:0] b;
always @(posedge clock or negedge reset)
if (!reset)
a = 0;
else
a = a + 1;
always @(posedge clock)
if (!reset)
b = 0;
else
b = a;
endmodule

3)what happens if a clk generated is from same always block.

module clk_dft(clk, a);
input wire clk;
input wire a;
reg b;
reg c;
always @(posedge clk)
b = clk & 1'b1;
always @(posedge b)
c = ~ a;
endmodule


These are the lint errors i was getting....

what exactly they refer to.....?

The Linting error is severe for above codes but above codes show not even a warning in synthesis.