CMOS Parasitic Bipolar min/max models?

[rcolbeck]

cmos parasitic

Hi, our 0.35um CMOS fab only gives us a nominal model for the parastic vertical pnp transistors. I'm looking for some guidance in creating my own min/max models. I expect the variation is fairly similar for TSMC, UMC, CSM, etc, so can anyone provide me with some scaling numbers? For instance I would include scaling factors for IS, NF, BF, etc, so that I have a min, typical and max model for the bipolar. Does anyone have models from their fab that has more than a typical model for the parasitic bipolars?

My motivation is that I want to better simulate our bandap and thermal sensor circuits.

Thanks, ..Roger

 

[huojinsi]

Re: CMOS min/max models?

u had better request Parasitic Bipolar min/max models which is supported by your foundry. Even if someone give u these models file, it is meaningless due to these models isn't compatible with your foundry.

 

[rcolbeck]

not available from our fab. They are not meaningless. The bipolar models are very similar. What I want to look at are the variations seen in the common factors such as Is, BF (Beta Forward) and NF (non ideality factor).

Roger

 

[swkimaz]

It is really hard to tell we can believe extracted spice models of parasitic bipolar from fabs. The best we can do(I believe it is) is make your own spice models(esp. critical parameters) from your lab by testing with simple circuit and then use these parameters for your spice simulation. That is best way to expect your simulation with chip test.