vlsi_whiz
Full Member level 4
fpga clock synchronization
Hi,
I've a problem with Altera FPGA based design. I'm workin on a processor-based board which uses the Cyclone FPGA and an IP core processor. Now the only other peripherals on the board are SDRAM, FLASH, MIL1553. The processor has built-in peripherals such as UART, Ethernet. The function of the FPGA is to conrtol the processor.
The problem faced is in clock synchronization. The internal PLL of the processor generates the core clock as well as SDRAM and SRAM clocks which are 1/4th and 1/8th of the core clock. The core clock is 200MHz.
The FPGA houses the logic to control the processor a main FSM, address decode logic, SDRAM controller..etc. I need to sync the FPGA FSM clock with the SRAM clock from the processor. The SRAM o/p from the processor is connected to the FPGA and the way I sync it is by passing the SRAM clock as the clock input to a D-FF and the FPGA clock of 25MHz to the D i/p. The ouput should be a clock that is in synch with the SRAM clock.
But what I get is a logic '1' o/p and no clock o/p. The SRAM clock is 25MHz and the FPGA logic clock is also 25MHz. Is it possible to sync the clocks or is there any other method of sync?? Can I use a 50MHz clock (SDRAM clock) from the processor to sync this FPGA clock??
Hi,
I've a problem with Altera FPGA based design. I'm workin on a processor-based board which uses the Cyclone FPGA and an IP core processor. Now the only other peripherals on the board are SDRAM, FLASH, MIL1553. The processor has built-in peripherals such as UART, Ethernet. The function of the FPGA is to conrtol the processor.
The problem faced is in clock synchronization. The internal PLL of the processor generates the core clock as well as SDRAM and SRAM clocks which are 1/4th and 1/8th of the core clock. The core clock is 200MHz.
The FPGA houses the logic to control the processor a main FSM, address decode logic, SDRAM controller..etc. I need to sync the FPGA FSM clock with the SRAM clock from the processor. The SRAM o/p from the processor is connected to the FPGA and the way I sync it is by passing the SRAM clock as the clock input to a D-FF and the FPGA clock of 25MHz to the D i/p. The ouput should be a clock that is in synch with the SRAM clock.
But what I get is a logic '1' o/p and no clock o/p. The SRAM clock is 25MHz and the FPGA logic clock is also 25MHz. Is it possible to sync the clocks or is there any other method of sync?? Can I use a 50MHz clock (SDRAM clock) from the processor to sync this FPGA clock??