Rx side of Aurora and clock synchronization

[msauer75]

Hello,

at the moment I implement my first design with aurora core. According to the manual I have to wait during clock synchronization time:

What will happen on the receiver side during the clock sync? Will the received data also hold?

Thank you for your help.

BR

martin sauer

 

[dpaul]

What will happen on the receiver side during the clock sync? Will the received data also hold?
Speaking generally on AXIS protocol, on the receive side, if you see the TREADY asserted low by the tx side (this is an input signal), then design the rx side logic such that TDATA values during this duration will not be registered.
btw - the spec diagram shows that Data3 is continued for the entire duration while TREADY is low.

 

[std_match]

The "clock compensation" cycles on the transmit side it to allow for the receiving end to have a slightly lower clock frequency.
Normally, the clock cycles on the TX side with tready = '0' will generate some clock cycles on the RX end with tvalid = '0'.
Since the clock frequencies can be a little different, the number of clock cycles on the TX side with tready = '0' can be different from the number of clock cycles on the RX side with tvalid = '0'.

 

[niciki]

I would suggest to generate example design from the Aurora IP Core (for more info find XAPP1193 and especially Figure 6: Open IP Example Design). Then find your answer by simulating the design.