Clock rule violation: C5 and C8, need help!

[riddhi.kapasi]

I am trying to insert scan in my design.
I am getting these 2 violation:
Level sensitive port captured data affected by new capture violations (C5)
Level sensitive port clock path affected by new capture violations (C8)

What is the method to get rid of them?

If anyone had smiliar violation and could share information about it, would be appreciated.

Let me know if more information about my design or script is req.
Thanks

---------- Post added at 21:14 ---------- Previous post was at 19:24 ----------

some help will be appreciated!

 

[riddhi.kapasi]

No one has any information about these violations?

 

[lostinxlation]

Whatever DFT tool you use, the violations come with instance name. Just look at the instnace in trouble in RTLs and trace the logic. It's much quicker and easier than just waiting for someone to chime in.

 

[rca]

ok, I beleived you used fastscan, that call is violation C5-C8,
First the fastscan documentation, indicate why the violation occurs, and how to solve it.
for example: to solve C8, set drc handling c8 ignore
As indicate by lostinxlation, the best solution is open the schematic to understand the problem, and fix it in RTL code, or force the "cell" to be process at X during the different phase.

 

[antique.2011]

You can also refer supportnet.mentor.com for a detailed explanation on C5 violation and how to solve it.
Hope this is use ful