Class C Power Amplifier Design using ATF 50189 GaAs pHEMT

[Power_Ani]

Hi everyone,
I am working on power amplifiers and I am using ATF 50189-BLK transistor from Avago Technologies. I am having some issues with this transistor while designing class C power amplifier. I am using the ADS 2017 design tool for the design. I have launched the Load Pull design guide of ADS to determine the optimum load impedance for the maximum PAE and maximum delivered load power. But when I am setting the bias for class C operation the load pull instrument shows unrealistic values of PAE and Gain. I am suspecting the load termination of the transistor is the main reason behind this. If anyone can suggest me the best possible load pull setup to get best results it will be very helpful for me. I have also gone through the example files but this transistor kept showing the same behavior for those setups too.

 

[G4BCH]

I can't help you with ADS load pull, but I hope you are not designig this into a new product as this part has been obsolete for some time.

 

[Power_Ani]

I can't help you with ADS load pull, but I hope you are not designig this into a new product as this part has been obsolete for some time.

I am designing this amplifier for my academic research purpose. For any product making purpose your suggestion is good.

 

[BigBoss]

C-Class Amplifiers are driven hard, you have probably forgotten to drive the amplifier with a higher driving level..

 

[Power_Ani]

C-Class Amplifiers are driven hard, you have probably forgotten to drive the amplifier with a higher driving level..

The transistor has a maximum input power level of 30 dBm and it has its OP1dB point as 29 dBm. So I have driven this transistor to its maximum limit but it is showing negative gain and negative PAE. That's why I was thinking that the the harmonic load terminations were not properly made. I have set the harmonic loads very large and again the results are not so promising. If you can suggest proper load pull setting for this configuration of operation with this transistor then I shall be grateful to you.

 

[BigBoss]

The transistor has a maximum input power level of 30 dBm and it has its OP1dB point as 29 dBm. So I have driven this transistor to its maximum limit but it is showing negative gain and negative PAE. That's why I was thinking that the the harmonic load terminations were not properly made. I have set the harmonic loads very large and again the results are not so promising. If you can suggest proper load pull setting for this configuration of operation with this transistor then I shall be grateful to you.

Post you ADS project file as .zap format and let me check where you did a mistake..

 

[Power_Ani]

Post you ADS project file as .zap format and let me check where you did a mistake..

I am sharing the archive file of my project. Please have a look and tell me where I am going wrong.View attachment Class_C_wrk.rar (Extracting the .rar file you will find the archived .7zads file of the project.)