Power_Ani
Newbie level 6
Hi everyone,
I am working on power amplifiers and I am using ATF 50189-BLK transistor from Avago Technologies. I am having some issues with this transistor while designing class C power amplifier. I am using the ADS 2017 design tool for the design. I have launched the Load Pull design guide of ADS to determine the optimum load impedance for the maximum PAE and maximum delivered load power. But when I am setting the bias for class C operation the load pull instrument shows unrealistic values of PAE and Gain. I am suspecting the load termination of the transistor is the main reason behind this. If anyone can suggest me the best possible load pull setup to get best results it will be very helpful for me. I have also gone through the example files but this transistor kept showing the same behavior for those setups too.
I am working on power amplifiers and I am using ATF 50189-BLK transistor from Avago Technologies. I am having some issues with this transistor while designing class C power amplifier. I am using the ADS 2017 design tool for the design. I have launched the Load Pull design guide of ADS to determine the optimum load impedance for the maximum PAE and maximum delivered load power. But when I am setting the bias for class C operation the load pull instrument shows unrealistic values of PAE and Gain. I am suspecting the load termination of the transistor is the main reason behind this. If anyone can suggest me the best possible load pull setup to get best results it will be very helpful for me. I have also gone through the example files but this transistor kept showing the same behavior for those setups too.