design_newbie
Newbie level 5
Hi all,
I am trying to design a circular buffer for a project, the project includes couple of modules and the way it should work is to receive a transport packet (188 bytes - which it receives the packet byte by byte) then in circular buffer when I receive 188 byte , the data_ready flag goes up and the next module will get the transport packet. I read the concept of circular buffer in Wikipedia and started my design.
Here is my code (I am using vivado 2018.3 for my design)
I wrote a testbench to see if my logic works. in the testbench first i tried a single write and a single read which seems working fine.Afterwards I tried to write in all locations of the RAM but it does not proceed after writing in first 11 locations ! Then I checked where does it stuck and it seems that the process stopped at line 74 of my code which is writing the data into the memory. I can't see the problem and I am a beginner. I tried to google it and even search here but I was not able to find a solution or improve my design !
Thank you in advance
I am trying to design a circular buffer for a project, the project includes couple of modules and the way it should work is to receive a transport packet (188 bytes - which it receives the packet byte by byte) then in circular buffer when I receive 188 byte , the data_ready flag goes up and the next module will get the transport packet. I read the concept of circular buffer in Wikipedia and started my design.
Here is my code (I am using vivado 2018.3 for my design)
Code:
[syntax=vhdl]library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity circular_buffer is
generic(
DATA_WIDTH : integer := 8;
ADDR_WIDTH : integer := 12 -- 2^12 = 4096 = 4k
);
Port (
-- Input clock domain
clk : in STD_LOGIC;
rstn : in STD_LOGIC;
wr_en : in STD_LOGIC;
wr_addr : in STD_LOGIC_VECTOR (ADDR_WIDTH-1 downto 0);
data_in : in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);
-- Output clock domain
-- s_clk : in STD_LOGIC;
rd_en : in STD_LOGIC;
rd_addr : in STD_LOGIC_VECTOR (ADDR_WIDTH-1 downto 0);
data_out : out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);
full : out STD_LOGIC;
empty : out STD_LOGIC;
data_ready : out STD_LOGIC
);
end circular_buffer;
architecture Behavioral of circular_buffer is
constant ts_packet_size : integer := 188;
signal byte_count : unsigned(ts_packet_size-1 downto 0) := (others => '0');
signal fifo_empty : std_logic := '1';
signal fifo_full : std_logic := '0';
signal rd_ptr : unsigned(ADDR_WIDTH-1 downto 0) := (others => '0');
signal wr_ptr : unsigned(ADDR_WIDTH-1 downto 0) := (others => '0');
type memory_type is array (0 to ADDR_WIDTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
signal memory : memory_type := (others => (others => '0'));
begin
full<= fifo_full;
empty <= fifo_empty;
process(clk, rstn)
begin
if rstn = '0' then
memory <= (others => (others => '0'));
rd_ptr <= (others => '0');
wr_ptr <= (others => '0');
fifo_full <= '0';
fifo_empty <= '1';
data_ready <= '0';
elsif rising_edge(clk) then
-- Write
if (wr_en = '1' and fifo_full = '0') then
memory(to_integer(wr_ptr)) <= data_in;
wr_ptr <= wr_ptr + 1;
byte_count <= byte_count + 1;
-- One packet is ready
if(byte_count = ts_packet_size) then
data_ready <= '1';
else
data_ready <= '0';
end if;
end if;
-- Read
if ( rd_en = '1' and fifo_empty = '1') then
data_out <= memory(to_integer(rd_ptr));
rd_ptr <= rd_ptr - 1;
end if;
-- Memory full
if (( wr_ptr + 1 = rd_ptr ) and (wr_en = '1') and (rd_en = '0')) then
fifo_full <= '1';
else
fifo_full <= '0';
end if;
-- Memory empty
if ((rd_ptr = wr_ptr) and (rd_en = '1') and (wr_en = '0')) then
fifo_empty <= '0';
else
fifo_empty <= '1';
end if;
end if;
end process;
end Behavioral;[/syntax]
I wrote a testbench to see if my logic works. in the testbench first i tried a single write and a single read which seems working fine.Afterwards I tried to write in all locations of the RAM but it does not proceed after writing in first 11 locations ! Then I checked where does it stuck and it seems that the process stopped at line 74 of my code which is writing the data into the memory. I can't see the problem and I am a beginner. I tried to google it and even search here but I was not able to find a solution or improve my design !
Thank you in advance