can clk multiplleing be done by DCM?

[milan.km]

HI
is there any way to multiply input clk by factor of pwers of two and use in some part of design?
as I searched i found that may be it could be done by DCM but i'm not so sure?
or is there any way to make clk's faster than input clk in our design.
thanks

 

[FvM]

Most likely yes, depends on the FPGA family.

 

[milan.km]

can u give me more explanation how it should be done?
thanks .i dont know even what to search
is it correct that i should do it with DCM ?
is there a way more simpler? because I didnt work with DCM yet
thanks

 

[FvM]

Which FPGA?

 

[milan.km]

in spartan 6.

 

[FvM]

If you need only a single derived (in this case N multiplied) clock, you can use the DCM_CLKGEN primitive, for multiple clocks PLL_BASE.

 

[milan.km]

i want a 4*clk and a 16*clk.clk in the input clock.would u explain more ? thanks

 

[TrickyDicky]

i want a 4*clk and a 16*clk.clk in the input clock.would u explain more ? thanks

How fast is the input clock?

 

[milan.km]

i dont know this,i didnt define it yet.
i want the input clk for importing each pixel to the design.i think 10 ns is ok.but i dont know how should I technically define it

 

[TrickyDicky]

Well, if your input clock is 100 Mhz (10ns) then there is no chance of getting a 16x clock, and 4x would be very difficult (if not impossible)
You should know the input clock rate from your project specifications.

 

[milan.km]

i want to process the video with 25 f/s .it means i have 40 ms for each img and each image is 256*256=65536.
it means that if each pixel comes at 40ms/65536 is ok.its equal to 0.61 us.
u mean that ok?

 

[ads-ee]

You should know the input clock rate from your project specifications.

As you mention pixels in your previous post. This usually means things like:

1920x1080 pixel display at 60 fps. i.e. 124.416 M pixels/sec

If you don't know the specifications of what the video/image resolution and frame rate (if it's video) are, then you need to find that out before trying to design anything.

 

[milan.km]

i want to do it for sth simpler like video 256*256 and 25 f/s.as i said I am a beginner in vhdl design.then i want to do sth more complicated like large images.

 

[TrickyDicky]

Whether you do it for 256x256 or larger video the principal (and probably the logic) is all the same. Just the clocks are faster.
The clock you're interested in is the pixel clock - for your 256x256 video the pixel clock is 16.4 Mhz (assuming no blanking)

Video in FPGA is quite straight forward. Why did you think you need 4x and 16x clocks?

 

[ads-ee]

I see you posted your specification.

It seems you only need a pixel clock of 1.6384 MHz or am I missing something?

Based on your other posts is the idea to expand a 256x256 image to 1024x1024 (that replicate stuff by 4 in each direction) or something? This is guess is why you are discussing a 4x clock and the image having 16x more pixels is why you are thinking of a 16x clock?

I think you need to come up with an architecture for the design instead of focusing on these low level details first. Then determine if a Spartan 6 can implement that architecture. Ideally you should be designing the architecture of your system based on pre-existing knowledge of the Spartan 6 FPGA architecture.

 

[milan.km]

for my previous post:wink:
i want to do interpolation for one image and and i want to give each input pixel 4 times with 4*clk and then buffer each line and read each line four times with 4*(4*clk)=16*clk to do the line interpolation.
I post the design too in the previous post as u said
https://www.edaboard.com/threads/346458/
thanks

 

[ads-ee]

Whether you do it for 256x256 or larger video the principal (and probably the logic) is all the same. Just the clocks are faster.
The clock you're interested in is the pixel clock - for your 256x256 video the pixel clock is 16.4 Mhz (assuming no blanking)

Video in FPGA is quite straight forward. Why did you think you need 4x and 16x clocks?

Tricky,

256x256x25=1.6384M how do you obtain 16.384 MHz, what am I missing here?

 

[milan.km]

i did the architecture of the design and i post it here
https://www.edaboard.com/threads/346458/
i dont have limitation on device.do u thinck changing spartan 6 with some sort of virtex will help me?

 

[ads-ee]

If my numbers are correct you're going to have problems with the input clock frequency as it's below the CLKIN_FREQ_DLL of 5 MHz for the DLL and far below the minimum PLL Finmin clock frequency of 19 MHz.

I think you should be running everything at the 26.2144 MHz (16x clock) and just generate enables at the lower rates. But that is part of the system design architecture, which despite the drawing in the other post doesn't appear to be well defined.

 

[milan.km]

I think you should be running everything at the 26.2144 MHz (16x clock) and just generate enables at the lower rates. But that is part of the system design architecture, which despite the drawing in the other post doesn't appear to be well defined.

thanks ,will u explain it more?
i am new to the design and i would appreciate if u explain how did u get 26.2144 MHz?

- - - Updated - - -

do u think its possible at all even by other designs(i mean interpolation by factor of 4).
the designd i draw was the only design cross to my mind.
do u think i should change it and do it by a factor of two maybe to be simpler and more realistic for fpga?