Cacence IC Design 5.0

[Amuro]

Do you install Cadence with root account? In the installation manual told that if you do like that, you may encounter the file privilege problem. And if you do so, try to install it again with normal account.

 

[lovelyic]

Do you install Cadence with root account? In the installation manual told that if you do like that, you may encounter the file privilege problem. And if you do so, try to install it again with normal account.

You can install it with normal account with no problem.

 

[yorkiny]

May be ur right.

 

[edacw1]

Surely. Virtuoso Tool is included in Cadence IC Design 5.0 Package .

 

[loverrf]

thank you for your advices.
I reinstalled cadence IC5 with user account.
it is working fine except one thing
I have gds importing problem.
when I import gds files. layout is not imported its exact layer. ie. all layers are imported some other layers.
I set display resource file (display.drf) but in vain.

can you tell how to solve it?

 

[cpsean]

Please set the right layer maping file in the
stream in form
the file example:

nwell 12
pdiff 12
....

 

[harkonnen]

I think it might not run on RedHat 7.3
Look at the .jpg from Vasily it says 7.2

 

[loverrf]

Hi. cpsean
thank you for reply.
can you tell me about layer mapping file in detail.
how can I make or extract mapping file?.

could you upload or PM me example mapping file.

thank you in advance.
loverrf

 

[cpsean]

Where did you get the gds file, and which process you use?

You should have correspond tech file and layer mapping file
from library vendor also
[/url]

 

[loverrf]

my gds file is exported from the ads2003a.
and gds file is imported very well into exact layers in the ic446 enviroments.

 

[loverrf]

hi
I have some problem.
in the icfb's main window, I cannot find "technology file" pull-down menu. except this, others such as File, Tools, Option, and Help Menu, are shown.
how can I solve this?.

loverrf.

 

[Petrovna]

Products included in Release-IC5141
Product # Product Name Version
111 Cadence(R) Design Framework II 5.1
12141 Cadence(R) Design Framework Integrator's Toolkit 5.1
14000 Preview Front-End Floorplanner System 5.1
14010 Preview Basic Floorplanner System 4.4.2
14020 Virtuoso(R) Preview 4.4.2
14040 Preview Timing Budgeter 5.1
14060 Smartpath 4.4.2
206 Virtuoso(R) Simulation Environment 5.1
207 Waveform 5.1
21060 Virtuoso(R) Schematic VHDL Interface 5.1
21400 Virtuoso(R) Schematic Editor Verilog(R) Interface 5.1
276 Virtuoso(R) Schematic Editor HSPICE Interface 5.1
283 Open Simulation System 5.1
300 Virtuoso(R) Layout Editor 5.1
3000 Virtuoso(R)-XL Layout Editor 5.1
3011 Virtuoso XL Basic 5.1.41
302 Virtuoso(R) Schematic Layout Option 5.1
305 Virtuoso(R) Compactor 5.1
311 Virtuoso(R) Layout Editor Turbo 5.1
3111 Virtuoso LE Turbo Basic 5.1.41
32100 Virtuoso(R) Analog Oasis Run-Time Option 5.1
32101 Cadence(R) OASIS for RFDE 5.1
32120 Virtuoso(R) Electronic Design for Manufacturability Option 5.1
32125 Cadence(R) Analog Corners Analysis Option 5.1
32130 Cadence(R) Analog Circuit Optimizer Option 5.1
32140 Cadence(R) Analog Mixed-Signal Simulation Interface Option 5.1
32150 Cadence(R) SPICE 5.1
32500 Virtuoso(R) Spectre(R) Circuit Simulator 5.1
32501 Virtuoso(R) Spectre Model Interface Option 5.1
32505 Spectre(R) Third-party Simulator Interface 1.0
32510 Spectre(R) Verilog-A Simulation Option 5.1
32520 Virtuoso(R) Spectre(R)-RF Simulation Option 5.1
32521 Spectre(R)/-RF - Cadence(R) SPW Model Link Option to Spectre(R) RF+G199 5.1
32530 Spectre(R)-RF IC Package Modeler Option 5.1
32760 Virtuoso(R) Analog HSPICE Interface Option 5.1
33015 Virtuoso(R) Core Optimizer 3.0
33016 Virtuoso(R) Core Characterizer 3.0
33301 Cadence(R) Analog Mixed-Signal Back-Annotation Interface Option 5.1
34500 Virtuoso(R) Schematic Editor 5.1
34510 Virtuoso(R) Analog Design Environment 5.1
34511 Spectre(R)-RF Substrate Coupling Analysis Option 5.1
34530 Cadence(R) Analog Distributed Processing Option 5.1
34570 Virtuoso(R) Analog VoltageStorm Option 4.1
34580 Virtuoso(R) Analog ElectronStorm Option 4.1
365 Dracula(R) Graphical User Interface 4.9
370 Virtuoso(R) Layout Synthesizer 5.1
37100 Switched Capacitor Layout Generators 5.1
374 Cell Optimization Option for Layout Synthesizer (370) 5.1
4000 Virtuoso(R) Chip Editor 5.1
501 ModuleMaker 5.1
5100 Virtuoso(R) Layout Migrate 5.1
550 Structure Compiler 5.1
570 Virtuoso(R) Schematic Composer to design compiler integration 5.1
681 Cadence(R) RC Network Reducer Option 3.0
70000 Virtuoso(R) AMS Designer Environment 1.0

70110 Dracula(R) Design Rule Checker 4.8
70120 Dracula(R) Layout Vs. Schematic Verifier 4.8
70130 Dracula(R) Parasitic Extractor 4.8
70510 Dracula(R) Physical Verification Suite 4.8
70520 Dracula(R) Physical Verification and Extraction Suite 4.8
71110 Diva(R) Design Rule Checker 4.4.5
71120 Diva(R) Layout Vs. Schematic Verifier 4.4.5
71130 Diva(R) Parasitic Extractor 4.4.5
71510 Diva(R) Physical Verification Suite 4.4.5
71520 Diva(R) Physical Verification and Extraction Suite 4.4.5
900 Cadence(R) SKILL Development Environment CAT 97B
90001 Virtuoso(R) Multi-mode Simulation 5.3
940 Virtuoso(R) EDIF 200 Reader 5.1
945 Virtuoso(R) EDIF 200 Writer 5.1
952 Virtuoso(R) EDIF 300 Connectivity Reader/Writer 5.1
953 Virtuoso(R) EDIF 300 Schematic Reader/Writer 5.1
972 SDLIN 5.1
974 CDLIN 5.1
BTAHVMOS Spectre(R) BTA HVMOS Model Not Applicable
BTASOI Spectre(R) BTA SOI Model Not Applicable
DSMODEL Spectre(R) DALLAS SEMICONDUCTOR Model Not Applicable
NTMODELS Spectre(R) Nortel Models Not Applicable
SCIMODEL Spectre Siemens Models Not Applicable
SPECTREBASIC Spectre(R)-Basic Advanced Circuit Simulator 5.1
STMODEL Spectre(R) ST Models Not Applicable
TW01 Cadence(R) team design manager 4.2
TW02 Cadence(R) team design project adminsitrator 4.2


©2003 Cadence Design Systems, Inc. All rights reserved. Trademarks | Privacy Policy

 

[sulifen]

I install the IC5032 on the redhat 7.3
it is working properly.
run icfb on X-term.
I import gds file after creating the library.
and open the layout file using Virtuoso.
but it is error message like this.
" layout editor capability is not enabled."
layout file is opened in the read-only mode.
what is problem ? how to solve this problem?

It maybe a license problem.
Make sure you've start the license daemon correct and check your $LM_LICENSE_FILE.

 

[gabi71ro]

hi
I have some problem.
in the icfb's main window, I cannot find "technology file" pull-down menu. except this, others such as File, Tools, Option, and Help Menu, are shown.
how can I solve this?.

loverrf.

The icfb mai menu is named CIW.
In CIW under Tools you will find Technolgy....
A new pop-up will appear.
Now you have the posibity to create a new tech lib or to edit the layers and so on....
When you want to left this menu, press Alt-F4 and don't press dismiss because you will dismiss all the modifications made.

Enjoy the Cadence tools and problems .

 

[chiara]

You had better use redhat 7.2 for more stable working.

if you have some license problem,
please try to use another port in the license file
eg 27001 or so.

and you can check which license is now availbale in the
design environment.

good luck

 

[visualart]

Products included in Release-IC5141
Product # Product Name Version
111 Cadence(R) Design Framework II 5.1
12141 Cadence(R) Design Framework Integrator's Toolkit 5.1
14000 Preview Front-End Floorplanner System 5.1
14010 Preview Basic Floorplanner System 4.4.2
14020 Virtuoso(R) Preview 4.4.2
14040 Preview Timing Budgeter 5.1
14060 Smartpath 4.4.2
206 Virtuoso(R) Simulation Environment 5.1
207 Waveform 5.1
21060 Virtuoso(R) Schematic VHDL Interface 5.1
21400 Virtuoso(R) Schematic Editor Verilog(R) Interface 5.1
276 Virtuoso(R) Schematic Editor HSPICE Interface 5.1
283 Open Simulation System 5.1
300 Virtuoso(R) Layout Editor 5.1
3000 Virtuoso(R)-XL Layout Editor 5.1
3011 Virtuoso XL Basic 5.1.41
302 Virtuoso(R) Schematic Layout Option 5.1
305 Virtuoso(R) Compactor 5.1
311 Virtuoso(R) Layout Editor Turbo 5.1
3111 Virtuoso LE Turbo Basic 5.1.41
32100 Virtuoso(R) Analog Oasis Run-Time Option 5.1
32101 Cadence(R) OASIS for RFDE 5.1
32120 Virtuoso(R) Electronic Design for Manufacturability Option 5.1
32125 Cadence(R) Analog Corners Analysis Option 5.1
32130 Cadence(R) Analog Circuit Optimizer Option 5.1
32140 Cadence(R) Analog Mixed-Signal Simulation Interface Option 5.1
32150 Cadence(R) SPICE 5.1
32500 Virtuoso(R) Spectre(R) Circuit Simulator 5.1
32501 Virtuoso(R) Spectre Model Interface Option 5.1
32505 Spectre(R) Third-party Simulator Interface 1.0
32510 Spectre(R) Verilog-A Simulation Option 5.1
32520 Virtuoso(R) Spectre(R)-RF Simulation Option 5.1
32521 Spectre(R)/-RF - Cadence(R) SPW Model Link Option to Spectre(R) RF+G199 5.1
32530 Spectre(R)-RF IC Package Modeler Option 5.1
32760 Virtuoso(R) Analog HSPICE Interface Option 5.1
33015 Virtuoso(R) Core Optimizer 3.0
33016 Virtuoso(R) Core Characterizer 3.0
33301 Cadence(R) Analog Mixed-Signal Back-Annotation Interface Option 5.1
34500 Virtuoso(R) Schematic Editor 5.1
34510 Virtuoso(R) Analog Design Environment 5.1
34511 Spectre(R)-RF Substrate Coupling Analysis Option 5.1
34530 Cadence(R) Analog Distributed Processing Option 5.1
34570 Virtuoso(R) Analog VoltageStorm Option 4.1
34580 Virtuoso(R) Analog ElectronStorm Option 4.1
365 Dracula(R) Graphical User Interface 4.9
370 Virtuoso(R) Layout Synthesizer 5.1
37100 Switched Capacitor Layout Generators 5.1
374 Cell Optimization Option for Layout Synthesizer (370) 5.1
4000 Virtuoso(R) Chip Editor 5.1
501 ModuleMaker 5.1
5100 Virtuoso(R) Layout Migrate 5.1
550 Structure Compiler 5.1
570 Virtuoso(R) Schematic Composer to design compiler integration 5.1
681 Cadence(R) RC Network Reducer Option 3.0
70000 Virtuoso(R) AMS Designer Environment 1.0

70110 Dracula(R) Design Rule Checker 4.8
70120 Dracula(R) Layout Vs. Schematic Verifier 4.8
70130 Dracula(R) Parasitic Extractor 4.8
70510 Dracula(R) Physical Verification Suite 4.8
70520 Dracula(R) Physical Verification and Extraction Suite 4.8
71110 Diva(R) Design Rule Checker 4.4.5
71120 Diva(R) Layout Vs. Schematic Verifier 4.4.5
71130 Diva(R) Parasitic Extractor 4.4.5
71510 Diva(R) Physical Verification Suite 4.4.5
71520 Diva(R) Physical Verification and Extraction Suite 4.4.5
900 Cadence(R) SKILL Development Environment CAT 97B
90001 Virtuoso(R) Multi-mode Simulation 5.3
940 Virtuoso(R) EDIF 200 Reader 5.1
945 Virtuoso(R) EDIF 200 Writer 5.1
952 Virtuoso(R) EDIF 300 Connectivity Reader/Writer 5.1
953 Virtuoso(R) EDIF 300 Schematic Reader/Writer 5.1
972 SDLIN 5.1
974 CDLIN 5.1
BTAHVMOS Spectre(R) BTA HVMOS Model Not Applicable
BTASOI Spectre(R) BTA SOI Model Not Applicable
DSMODEL Spectre(R) DALLAS SEMICONDUCTOR Model Not Applicable
NTMODELS Spectre(R) Nortel Models Not Applicable
SCIMODEL Spectre Siemens Models Not Applicable
SPECTREBASIC Spectre(R)-Basic Advanced Circuit Simulator 5.1
STMODEL Spectre(R) ST Models Not Applicable
TW01 Cadence(R) team design manager 4.2
TW02 Cadence(R) team design project adminsitrator 4.2


©2003 Cadence Design Systems, Inc. All rights reserved. Trademarks | Privacy Policy

Is it all?
what does the LDV and DSM include?
Tia

 

[krewe]

Use "configure" script in $<CDSDIR>/share/license and follow its guide. You will need root password in order to add start script of the license daemon.

I'm sorry but could you describe it in detail!??
I'm a beginner in IC-design, thanks