[SOLVED] bus driving problem..

[fatihtir1]

Hello,

I use picoblaze for sram read/write operations. I see a problem in simulation of sram_ad writing (below code). 16th bit of Sram_ad ( sram_ad(16) ) is seen as X in the simulation, no problem for the other bits. But i drive out_port to all bits of sram_ad by using 3 ports. What is, do you think, the problem.

Regards.

Note: my sram_ad is 18 bits.


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Code VHDL - [expand]
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output_ports: process(clk)
  begin
 
    if clk'event and clk='1' then
      if write_strobe='1' then
 
        -- Adres [17:16] port C0 hex
        if port_id(7 downto 6)="11" then
          sram_ad(17 downto 16) <= out_port(1 downto 0);
        end if;
 
        -- Adres [15:8] port 80 hex
        if port_id(7 downto 6)="10" then
          sram_ad(15 downto 8) <= out_port;
        end if;
          
          -- Adres [7:0] port 40 hex
        if port_id(7 downto 6)="01" then
          sram_ad(7 downto 0) <= out_port;
        end if;

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---------- Post added at 09:01 ---------- Previous post was at 07:06 ----------

Sorry for the question and taking your time.

I noticed I didn't changed a previous driving of these bits. Somewhere on the code:

sram_ad(17 downto 16) <= "00";

I apologize from all you.


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